參數(shù)資料
型號(hào)： HYB39S512400ATL
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit Synchronous DRAM
中文描述： 512兆位同步DRAM
文件頁(yè)數(shù)： 25/28頁(yè)
文件大?。?/td> 718K
代理商： HYB39S512400ATL
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Electrical Characteristics
Data Sheet
25
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
Read Cycle
Data Out Hold Time
Data Out to Low Impedance
Time
Data Out to High Impedance
Time
DQM Data Out Disable Latency
t
OH
t
LZ
3
1
–
–
3
1
–
–
3
0
–
–
ns
ns
3)6)
t
HZ
3
7
3
7
3
8
ns
t
DQZ
–
2
–
2
–
2
CLK
Write Cycle
Last Data Input to Precharge
(Write without AutoPrecharge)
Last Data Input to Activate (Write
with Auto Precharge)
DQM Write Mask Latency
t
WR
14
–
15
–
16
–
ns
8)
t
DAL(min.)
(
t
WR
/
t
CK
) + (
t
RP
/
t
CK
)
CLK
9)
t
DQW
0
–
0
–
0
–
CLK
1)
T
A
= 0 to 70
C;
V
SS
= 0 V,
V
DD
,
V
DDQ
= 3.3 V ± 0.3 V,
t
T
= 1 ns
2) For proper power-up see the operation section of this data sheet.
3) AC timing tests for LV-TTL versions have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between
V
IH
and
V
IL
. All AC measurements assume
T
T
= 1 ns with the AC output
load circuit shown in figure below. Specified tac and toh parameters are measured with a 50 pF only, without any resistive
termination and with an input signal of 1V / ns edge rate between 0.8 V and 2.0 V.
4) If clock rising time is longer than 1 ns, a time (
T
T
/2 - 0.5) ns has to be added to this parameter.
5) if
T
T
is longer than 1 ns, a time (
T
T
- 1) ns has to be added to this parameter.
6) Access time from clock tac is 4.6 ns for PC133 components with no termination and 0 pF load, Data out hold time toh is
1.8 ns for PC133 components with no termination and 0 pF load.
7) This parameter determines the minimum required number of clock cycles as follows: the required number of clock cycles
is given by the value of the specified parameter divided by the period of the clock. Non-integer values must be rounded up
to the next greater integer value.
8) It is recommended to use two clock cycles between the last data-in and the precharge command in case of a write
command without Auto-Precharge. One clock cycle between the last data-in and the precharge command is also
supported, but restricted to cycle times tck greater or equal the specified
t
WR
value, where
t
CK
is equal to the actual system
clock time.
9) When a Write command with AutoPrecharge has been issued, a time of
t
DAL(min.)
has be fullfilled before the next Activate
Command can be applied. For each of the terms, if not already an integer, round up to the next highest integer. tck is equal
to the actual system clock time.
Table 12
Parameter
AC Characteristics
1)2)3)
Symbol
–
7
–
7.5
–
8
Unit
Notes
PC133-222
min.
PC133-333
min.
PC100-222
min.
max.
max.
max.
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