參數(shù)資料
型號(hào)： HYB39S512400ATL
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit Synchronous DRAM
中文描述： 512兆位同步DRAM
文件頁(yè)數(shù)： 20/28頁(yè)
文件大?。?/td> 718K
代理商： HYB39S512400ATL
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Functional Description
Data Sheet
20
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O
organization and column addressing. Full page burst operation does not self terminate once the burst length has
been reached. In other words, unlike burst lengths of 2, 4 and 8, full page burst continues until it is terminated
using another command.
Similar to the page mode of conventional DRAMs, burst read or write accesses on any column address are
possible once the RAS cycle latches the sense amplifiers. The maximum
t
RAS
or the refresh interval time limits the
number of random column accesses. A new burst access can be done even before the previous burst ends. The
interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining
addresses are overridden by the new address with the full burst length. An interrupt which accompanies an
operation change from a read to a write is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With
the programmed burst length, alternate access and precharge operations on two or more banks can realize fast
serial data access modes among many different pages. Once two or more banks are activated, column to column
interleave operation can be performed between different pages.
3.5.2
DQM has two functions for data I/O read and write operations. During reads, when it turns to “high“ at a clock
timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency
t
DQZ
). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock
is prohibited (DQM Write Mask Latency
t
DQW
= zero clocks).
DQM Function
3.5.3
During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock
and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend
Latency
t
CSL
).
Suspend Mode
3.5.4
In order to reduce standby power consumption, a power down mode is available. All banks must be precharged
and the necessary Precharge delay (
t
RP
) must occur before the SDRAM can enter the Power Down mode. Once
the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated
off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power
Down mode longer than the Refresh period (
t
REF
) of the device. Exit from this mode is performed by taking CKE
“high“. One clock delay is required for Power Down mode entry and exit.
Power Down
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PDF描述
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