參數(shù)資料
型號(hào): HYB39S512400ATL
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit Synchronous DRAM
中文描述: 512兆位同步DRAM
文件頁(yè)數(shù): 24/28頁(yè)
文件大?。?/td> 718K
代理商: HYB39S512400ATL
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Electrical Characteristics
Data Sheet
24
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
4.2
AC Characteristics
Table 12
Parameter
AC Characteristics
1)2)3)
Symbol
7
7.5
8
Unit
Notes
PC133-222
min.
PC133-333
min.
PC100-222
min.
max.
max.
max.
Clock and Clock Enable
Clock Cycle Time
CAS Latency = 3
CAS Latency = 2
Clock Frequency
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
CAS Latency = 3
CAS Latency = 2
Clock High Pulse Width
Clock Low Pulse Width
Transition time
t
CK
7
7.5
7.5
10
8
10
ns
ns
t
CK
143
133
133
100
125
100
MHz
MHz
t
AC
5.4
5.4
5.4
6
6
6
ns
ns
3)4)5)
t
CH
t
CL
t
T
2.5
2.5
0.3
1.2
2.5
2.5
0.3
1.2
3
3
0.5
10
ns
ns
ns
Setup and Hold Times
Input Setup Time
Input Hold Time
CKE Setup Time
CKE Hold Time
Mode Register Set-up to Active
delay
Power Down Mode Entry Time
t
IS
t
IH
t
CK
t
CKH
t
RSC
1.5
0.8
1.5
0.8
2
1.5
0.8
1.5
0.8
2
2
1
2
1
2
ns
ns
ns
ns
CLK
6)
6)
6)
6)
t
SB
0
7
0
7.5
0
8
ns
Common Parameters
Row to Column Delay Time
Row Precharge Time
Row Active Time
Row Cycle Time
Row Cycle Time during Auto
Refresh
Activate(a) to Activate(b)
Command period
CAS(a) to CAS(b) Command
period
t
RCD
t
RP
t
RAS
t
RC
t
RFC
15
15
37
60
63
100k
20
20
45
67
67
100k
20
20
48
70
70
100k
ns
ns
ns
ns
ns
7)
7)
7)
7)
t
RRD
14
15
16
ns
7)
t
CCD
1
1
1
CLK
Refresh Cycle
Refresh Period (8192 cycles)
Self Refresh Exit Time
t
REF
t
SREX
1
64
1
64
1
64
ms
CLK
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