參數(shù)資料
型號(hào): HYB39S512400ATL
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit Synchronous DRAM
中文描述: 512兆位同步DRAM
文件頁數(shù): 15/28頁
文件大小: 718K
代理商: HYB39S512400ATL
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X
H
X
L
X
H
X
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Functional Description
Data Sheet
15
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
3
Functional Description
3.1
Operation Definition
All SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge
of the clock. The following list shows the truth table for the operation commands.
Table 4
Operation
Truth Table: Operation Command
Devics State
CKE
n-1
1)2)
H
H
H
H
H
1) V = Valid, x = Don’t Care, L = Low Level, H = High Level
2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are
provided.
3) This is the state of the banks designated by BA0, BA1 signals.
4) Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in
clock suspend mode.
CKE
n
1)2)
X
X
X
X
X
DQM
1)2)
BA0
BA1
1)2)
V
V
X
V
V
AP=
A10
1)2)
V
L
H
L
H
Addr
1)2)
CS
1)2)
RAS
1)2)
CAS
1)2)
WE
1)2)
Bank Active
Bank Precharge
Precharge All
Write
Write with Autopre-
charge
Read
Read with Autopre-
charge
Mode Register Set
No Operation
Burst Stop
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Idle
3)
Any
Any
Active
3)
Active
3)
X
X
X
X
X
V
X
X
V
V
L
L
L
L
L
L
L
L
H
H
H
H
H
L
L
H
L
L
L
L
Active
3)
Active
3)
H
H
X
X
X
X
V
V
L
H
V
V
L
L
H
H
L
L
H
H
Idle
Any
Active
Any
Idle
Idle
Idle
(Self Refr.)
H
H
H
H
H
H
L
X
X
X
X
X
X
V
X
X
X
X
X
X
V
X
X
X
X
X
X
V
X
X
X
X
X
X
L
L
L
H
L
L
H
L
X
L
H
H
X
L
L
X
H
X
L
H
H
X
L
L
X
H
X
L
H
L
X
H
H
X
X
X
Clock Suspend
Entry
Power Down Entry
(Precharge or active
standby)
Active
L
H
X
X
X
X
Idle
H
L
X
X
X
X
H
X
X
X
Active
4)
Active
Any
(Power Down)
L
X
H
L
X
H
X
X
H
X
H
X
X
H
X
H
X
X
L
X
Clock Suspend Exit
Power Down Exit
L
L
H
H
X
X
X
X
X
X
X
X
Data Write/Output
Enable
Data Write/Output
Disable
Active
H
X
L
X
X
X
Active
H
X
H
X
X
X
X
X
X
X
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