參數(shù)資料
型號： HYB39S512400ATL
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit Synchronous DRAM
中文描述： 512兆位同步DRAM
文件頁數(shù)： 17/28頁
文件大?。?/td> 718K
代理商： HYB39S512400ATL
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Functional Description
Data Sheet
17
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
MR
Mode Register Definition
(BA[1:0] = 00
B
)
BA1
BA0
A12
A13
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
MODE
CL
BT
BL
reg. addr
w
w
w
w
Field
BL
Bits
[2:0]
Type
w
Description
Burst Length
Number of sequential bits per DQ related to one read/write command
Note:All other bit combinations are RESERVED
000 1
001 2
010 4
011 8
111 Full Page
Burst Type
See
Table 5
for internal address sequence of low order address bits.
0
Sequential
1
Interleaved
CAS Latency
Number of full clocks from read command to first data valid window.
Note:All other bit combinations are RESERVED
BT
3
w
CL
[6:4]
w
010 2
011 3
Operating Mode
Note:All other bit combinations are RESERVED.
Operating
Mode
[13:7] w
0
1
burst read / burst write
burst read / single write
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