參數(shù)資料
型號: HYB39S512400ATL
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit Synchronous DRAM
中文描述: 512兆位同步DRAM
文件頁數(shù): 12/28頁
文件大?。?/td> 718K
代理商: HYB39S512400ATL
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Pin Configuration
Data Sheet
12
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
2.3
Block Diagrams
Figure 2
Block Diagram for 128M
×
4 SDRAM ( 13 / 12 / 2 addressing)
M em ory
Array
Bank 1
x 4 Bit
M em ory
Array
Bank 2
x 4 Bit
M em ory
Array
Bank 3
x 4 Bit
Colum n Address
Counter
Row
Decoder
M em ory
Array
Bank 0
x 4 Bit
C
S
Row
Decoder
S
Row
Decoder
Row
Decoder
C
S
Row Address
Buffer
Colum n Address
Buffer
Refresh Counter
S
A0 - A12,
BA0, BA1
A0 - A9, AP,A11,A12
BA0, BA1
Colum n Addresses
Row Addresses
Input Buffer
O utput Buffer
DQ 0 - DQ 3
Control Logic &
Tim ing G enerator
C
C
C
R
C
W
D
C
C
8192
x 4096
8192
x 4096
8192
x 4096
8192
x 4096
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