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參數(shù)資料
| 型號： | HYB39S512400ATL |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512-Mbit Synchronous DRAM |
| 中文描述： | 512兆位同步DRAM |
| 文件頁數(shù)： | 18/28頁 |
| 文件大小： | 718K |
| 代理商： | HYB39S512400ATL |
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HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Functional Description
Data Sheet
18
Rev. 1.3, 2004-03
10082003-L1GD-PVI5
3.3.1
Burst Length
Note:
1. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the
block.
3. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within
the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps
within the block.
3.4
Commands
Refresh Mode
SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS
refresh of conventional DRAMs. All banks must be precharged before applying any refresh mode. An on-chip
address counter increments the word and the bank addresses and no bank information is required for either
refresh mode.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a
positive clock transition. The mode restores word line after the refresh and no external precharge command is
necessary. A minimum
t
RC
time is required between two automatic refreshes in a burst refresh mode. The same
rule applies to any access command after the automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. The mode restores the word lines after RAS,
CAS, and CKE are low and WE is high at a positive clock transition. All external control signals including the clock
are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit
command, at least one
t
RC
delay is required prior to any access command.
Table 5
Burst Length
Burst Length and Sequence
Starting Column Address
A2
A1
Order of Accesses Within a Burst
Type = Sequential
0-1
1–0
0–1–2–3
1–2–3–0
2–3–0–1
3–0–1–2
0–1–2–3–4–5–6–7
1–2–3–4–5–6–7–0
2–3–4–5–6–7–0–1
3–4–5–6–7–0–1–2
4–5–6–7–0–1–2–3
5–6–7–0–1–2–3–4
6–7–0–1–2–3–4–5
7–0–1–2–3–4–5–6
Cn, Cn+1, Cn+2 ....
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
n
Type = Interleaved
0–1
1–0
0–1–2–3
1–0–3–2
2–3–0–1
3–2–1–0
0–1–2–3–4–5–6–7
1–0–3–2–5–4–7–6
2–3–0–1–6–7–4–5
3–2–1–0–7–6–5–4
4–5–6–7–0–1–2–3
5–4–7–6–1–0–3–2
6–7–4–5–2–3–0–1
7–6–5–4–3–2–1–0
not supported
2
4
0
0
1
1
0
0
1
1
0
0
1
1
n
8
0
0
0
0
1
1
1
1
n
Full Page
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