參數(shù)資料
型號(hào)： HYB18T512160AF-3.7
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit DDR2 SDRAM
中文描述： 512兆位DDR2 SDRAM的
文件頁數(shù)： 91/117頁
文件大?。?/td> 2102K
代理商： HYB18T512160AF-3.7
Data Sheet
91
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Currents Measurement Specifications and Conditions
6
Currents Measurement Specifications and Conditions
Table 44
Parameter
Operating Current -
One bank Active - Precharge
t
CK
=
t
CK(IDD)
,
t
RC
=
t
RC(IDD)
,
t
RAS
=
t
RAS.MIN(IDD)
, CKE is HIGH, CS is HIGH between valid
commands. Address and control inputs are switching; Databus inputs are switching.
Operating Current - One bank Active - Read - Precharge
I
OUT
= 0 mA, BL = 4,
t
CK
=
t
CK(IDD)
,
t
RC
=
t
RC(IDD)
,
t
RAS
=
t
RAS.MIN(IDD)
,
t
RCD
=
t
RCD(IDD)
, AL = 0,
CL = CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control
inputs are switching; Databus inputs are switching.
Precharge Power-Down Current
All banks idle; CKE is LOW;
t
CK
=
t
CK(IDD)
;Other control and address inputs are stable; Data
bus inputs are floating
.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CK(IDD)
; Other control and address inputs are
switching, Data bus inputs are switching
.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
t
CK
=
t
CK(IDD)
; Other control and address inputs are
stable, Data bus inputs are floating.
Active Power-Down Current
All banks open;
t
CK
=
t
CK(IDD)
, CKE is LOW; Other control and address inputs are stable; Data
bus inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
Active Power-Down Current
All banks open;
t
CK
=
t
CK(IDD)
, CKE is LOW; Other control and address inputs are stable, Data
bus inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
Active Standby Current
All banks open;
t
CK
=
t
CK(IDD)
;
t
RAS
=
t
RAS.MAX(IDD)
,
t
RP
=
t
RP(IDD)
; CKE is HIGH, CS is HIGH
between valid commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
(IDD)
;
t
CK
=
t
CK(IDD)
;
t
RAS
=
t
RAS.MAX.(IDD)
,
t
RP
=
t
RP(IDD)
; CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
I
OUT
= 0 mA.
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
(IDD)
;
t
CK
=
t
CK(IDD)
;
t
RAS
=
t
RAS.MAX(IDD)
,
t
RP
=
t
RP(IDD)
; CKE is HIGH, CS is HIGH between valid
commands. Address inputs are switching; Data Bus inputs are switching;
Burst Refresh Current
t
CK
=
t
CK(IDD)
, Refresh command every
t
RFC
=
t
RFC(IDD)
interval, CKE is HIGH, CS is HIGH
between valid commands, Other control and address inputs are switching, Data bus inputs
are switching.
Distributed Refresh Current
t
CK
=
t
CK(IDD)
, Refresh command every
t
REFI
= 7.8
μ
s interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are switching, Data bus inputs
are switching.
I
DD
Measurement Conditions
Symbol Note
I
DD0
1)2)3)4)5)6)
I
DD1
1)2)3)4)5)6)
I
DD2P
1)2)3)4)5)6)
I
DD2N
1)2)3)4)5)6)
I
DD2Q
1)2)3)4)5)6)
I
DD3P(0)
1)2)3)4)5)6)
I
DD3P(1)
1)2)3)4)5)6)
I
DD3N
1)2)3)4)5)6)
I
DD4R
1)2)3)4)5)6)
I
DD4W
1)2)3)4)5)6)
I
DD5B
1)2)3)4)5)6)
I
DD5D
1)2)3)4)5)6)
相關(guān)PDF資料
PDF描述
HYB18T512160AF-3S 512-Mbit DDR2 SDRAM
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HYB18T512400AF-3S 512-Mbit DDR2 SDRAM
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