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| 型號： | HYB18T512160AF-3.7 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 512-Mbit DDR2 SDRAM |
| 中文描述： | 512兆位DDR2 SDRAM的 |
| 文件頁數(shù)： | 46/117頁 |
| 文件大?。?/td> | 2102K |
| 代理商： | HYB18T512160AF-3.7 |
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HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Data Sheet
46
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
T4
3.15
Read and Write Commands and Access Modes
After a bank has been activated, a read or write cycle
can be executed. This is accomplished by setting RAS
HIGH, CS and CAS LOW at the clock’s rising edge. WE
must also be defined at this time to determine whether
the access cycle is a read operation (WE HIGH) or a
write operation (WE LOW). The DDR2 SDRAM
provides a wide variety of fast access modes. A single
Read or Write Command will initiate a serial read or
write operation on successive clock cycles at data rates
of up to 533 Mb/sec/pin for main memory. The
boundary of the burst cycle is restricted to specific
segments of the page length.
For example, the 32 Mbit
×
4 I/O
× 4
Bank chip has a
page length of 2048 bits (defined by CA[11, 9:0]).
In case of a 4-bit burst operation (burst length = 4) the
page length of 2048 is divided into 512 uniquely
addressable segments (4-bits
×
4 I/O each). The 4-bit
burst operation will occur entirely within one of the 512
segments (defined by CA[8:0]) starting with the column
address supplied to the device during the Read or Write
Command (CA[11, 9:0]). The second, third and fourth
access will also occur within this segment, however,
the burst order is a function of the starting address, and
the burst sequence.
In case of a 8-bit burst operation (burst length = 8) the
page length of 2048 is divided into 256 uniquely
addressable segments (8-bits
×
4 I/O each). The 8-bit
burst operation will occur entirely within one of the 256
segments (defined by CA[7:0]) beginning with the
column address supplied to the device during the Read
or Write Command (CA[11, 9:0]).
A new burst access must not interrupt the previous 4 bit
burst operation in case of BL = 4 setting. Therefore the
minimum CAS to CAS delay (
t
CCD
) is a minimum of 2
clocks for read or write cycles.
For 8 bit burst operation (BL = 8) the minimum CAS to
CAS delay (
t
CCD
) is 4 clocks for read or write cycles.
Burst interruption is allowed with 8 bit burst operation.
For details see Chapter 3.20.
Figure 18
Read Timing Example
CL = 3, AL = 0, RL = 3, BL = 4
NOP
NOP
NOP
NOP
NOP
READ A
T0
T2
T1
T3
T5
T6
T7
T12
CMD
DQ
RB
DQS,
DQS
READ B
NOP
Dout A0
Dout A1
Dout A2
Dout A3 Dout B0
Dout B1
Dout B2
Dout B3
Dout C0
Dout C1
Dout C2
Dout C3
NOP
READ C
tCCD
tCCD
CK, CK
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參數(shù)描述 |
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| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
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| HYB18T512400BF-3S | 制造商:Qimonda 功能描述: |
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| HYB18T512800BF-2.5 | 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF) |
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