參數(shù)資料
型號(hào)： HYB18T512160AF-3.7
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit DDR2 SDRAM
中文描述： 512兆位DDR2 SDRAM的
文件頁數(shù)： 74/117頁
文件大小： 2102K
代理商： HYB18T512160AF-3.7
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Functional Description
Data Sheet
74
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
3.27
Input Clock Frequency Change
During operation the DRAM input clock frequency can
be changed under the following conditions:
During Self-Refresh operation
DRAM is in Precharge Power-down mode and ODT
is completely turned off.
In the Precharge Power-down mode the DDR2-
SDRAM has to be in Precharged Power-down mode
and idle. ODT must be already turned off and CKE must
be at a logic LOW state. After a minimum of two clock
cycles after
t
RP
and
t
AOFD
have been satisfied the input
clock frequency can be changed. A stable new clock
frequency has to be provided, before CKE can be
changed to a HIGH logic level again. After
t
XP
has been
satisfied a DLL RESET command via EMRS(1) has to
be issued. During the following DLL re-lock period of
200 clock cycles, ODT must remain off. After the DLL-
re-lock period the DRAM is ready to operate with the
new clock frequency.
Figure 62
Input Frequency Change Example during Precharge Power-Down mode
3.28
Asynchronous CKE LOW Reset Event
In a given system, Asynchronous Reset event can
occur at any time without prior knowledge. In this
situation, memory controller is forced to drop CKE
asynchronously LOW, immediately interrupting any
valid operation. DRAM requires CKE to be maintained
HIGH for all valid operations as defined in this data
sheet. If CKE asynchronously drops LOW during any
valid operation, the DRAM is not guaranteed to
preserve the contents of the memory array. If this event
occurs, the memory controller must satisfy a time delay
(
t
DELAY
) before turning off the clocks. Stable clocks must
exist at the input of DRAM before CKE is raised HIGH
again. The DRAM must be fully re-initialized as
described the initialization sequence (Power On and
Initialization, step 4 through 13). DRAM is ready for
normal operation after the initialization sequence. See
Chapter 7 for
t
DELAY
specification.
Figure 63
Asynchronous Low Reset Event
NOP
NOP
T0
T2
T1
T3
T4
Tx
Tx+1
Ty
CMD
NOP
NOP
NOP
NOP
NOP
DLL
RESET
Ty+2
Ty+3
CKE
Frequency Change
occurs here
NOP
NOP
Frequ.Ch.
Tz
tXP
Stable new clock
before power-down exit
CK, CK
tRP
tAOFD
Minimum 2 clocks
required before
changing the frequency
Ty+1
NOP
Valid
Command
200 clocks
ODT is off during
DLL RESET
CKE
CKE drops low due to an
asynchronous reset event
Clocks can be turned off after
this point
tdelay
CK, CK
stable clocks
相關(guān)PDF資料
PDF描述
HYB18T512160AF-3S 512-Mbit DDR2 SDRAM
HYB18T512400AF-3 512-Mbit DDR2 SDRAM
HYB18T512400AF-3S 512-Mbit DDR2 SDRAM
HYB18T512800AF-3 512-Mbit DDR2 SDRAM
HYB18T512800AF-3.7 512-Mbit DDR2 SDRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:60 系列:- 格式 - 存儲(chǔ)器:EEPROMs - 串行 存儲(chǔ)器類型:EEPROM 存儲(chǔ)容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
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