參數(shù)資料
型號: HYB18T512160AF-3.7
廠商: INFINEON TECHNOLOGIES AG
英文描述: 512-Mbit DDR2 SDRAM
中文描述: 512兆位DDR2 SDRAM的
文件頁數(shù): 18/117頁
文件大小: 2102K
代理商: HYB18T512160AF-3.7
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
Pin Configuration and Block Diagrams
Data Sheet
18
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
Power Supply
B3
DM
I
SSTL
Data Mask
Note:DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH coincident with that
input data during a write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading. LDM and UDM
are the input mask signals for
×
16 components and control
the lower or upper bytes. For
×
8 components the data mask
function is disabled, when RDQS/RDQS are enabled by
EMRS(1) command.
Data Mask
×
16 organization
B3
F3
Power Supplies
×
4/
×
8
16 organizations
A9,C1,C3,C7,
C9
A1
V
DD
A7,B2,B8,D2,
D8
A3,E3
V
SS
Power Supplies
×
4/
×
8 organizations
E2
V
REF
E1
V
DDL
E9,H9,L1
V
DD
E7
V
SSDL
J1,K9
V
SS
Power Supplies
×
16 organization
J2
V
REF
E9, G1, G3,
G7, G9
J1
V
DDL
E1, J9, M9, R1
V
DD
E7, F2, F8, H2,
H8
J7
V
SSDL
J3,N1,P9
V
SS
Not Connected
×
4/
×
8 organizations
G1, L3,L7, L8
NC
UDM
LDM
I
I
SSTL
SSTL
Data Mask Upper Byte
Data Mask Lower Byte
V
DDQ
PWR
I/O Driver Power Supply
PWR
PWR
Power Supply
Power Supply
V
SSQ
PWR
AI
PWR
PWR
PWR
PWR
I/O Reference Voltage
Power Supply
Power Supply
Power Supply
Power Supply
AI
PWR
I/O Reference Voltage
I/O Driver Power Supply
V
DDQ
PWR
PWR
PWR
Power Supply
Power Supply
Power Supply
V
SSQ
PWR
PWR
Power Supply
Power Supply
NC
Not Connected
Note:No internal electrical connection is present
Not Connected
×
4 organization
A2, B1, B9,
D1, D9
NC
NC
Not Connected
Table 4
Ball#/Pin#
Pin Configuration of DDR SDRAM
Name
Pin
Type
Buffer
Type
Function
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