參數(shù)資料
型號： HYB18T512160AF-3.7
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit DDR2 SDRAM
中文描述： 512兆位DDR2 SDRAM的
文件頁數(shù)： 108/117頁
文件大?。?/td> 2102K
代理商： HYB18T512160AF-3.7
HYB18T512[40/80/16]0AF–[3/3S/3.7/5]
512-Mbit DDR2 SDRAM
AC Timing Measurement Conditions
Data Sheet
108
Rev. 1.3, 2005-01
09112003-SDM9-IQ3P
8.3.4
Setup (
t
IS
&
t
DS
) nominal Slew Rate for a rising signal is
defined as the Slew Rate between the last crossing of
V
REF(dc)
and the first crossing of
V
IH(ac).MIN
. Setup (
t
IS
&
t
DS
) nominal Slew Rate for a falling signal is defined as
the Slew Rate between the last crossing of
V
REF(dc)
and
the first crossing of
V
IL(ac).MAX
. If the actual signal is
always earlier than the nominal Slew Rate line between
shaded ‘
V
REF(dc)
to ac region’, use nominal Slew Rate
for derating value (see
Figure 76
). If the actual signal
is later than the nominal Slew Rate line anywhere
between shaded ‘
V
REF(dc)
to ac region’, the Slew Rate of
a tangent line to the actual signal from the ac level to dc
Slew Rate Definition for Input and Data Setup and Hold Times
level is used for derating value.(see
Figure 77
) Hold
(
t
IH
&
t
DH
) nominal Slew Rate for a rising signal is
defined as the Slew Rate between the last crossing of
V
IL(dc).MAX
and the first crossing of
V
REF(dc)
. Hold (
t
IH
&
t
DH
) nominal Slew Rate for a falling signal is defined as
the Slew Rate between the last crossing of
V
IH(dc).MIN
and the first crossing of
V
REF(dc)
. If the actual signal is
always later than the nominal Slew Rate line between
shaded ‘dc to
V
REF
region’, use nominal Slew Rate for
derating value (see
Figure 76
). If the actual signal is
earlier than the actual signal from the dc level to
V
REF
level is used for derating value (see
Figure 77
)
Figure 76
Slew Rate Definition Nominal
3ETUP 3LEW 2ATE
62%&D C
6), AC MAX
$ELTA 4&3
FALLING SIGNAL
3ETUP 3LEW 2ATE
6)( AC MIN 62%& DC
$ELTA 423
RISING SIGNAL
(O LD 3LEW 2ATE
62%& DC
6), DC MAX
$ELTA 42(
RISING SIGNAL
(OLD3 LEW 2ATE
6)( DC MIN 62%& DC
$ELTA 4&(
FALLING SIGNAL
6
33
6
), AC
MAX
6
), DC
MAX
6
2%&
6
)( DC
MIN
6
$$1
6
)( AC
MIN
$ELTA 4&3
$ELTA 42(
$E LTA 4&(
$ELTA 423
DC TO 62% &
REGION
62% & TO AC
REGION
DC TO 62%&
REGION
62% & TO AC
REGION
#+ #+ FOR T)3 AND T)(
$13 $13 FOR T$3 AND T$(
T
)3
T
$3
T
)(
T
$(
T
)3
T
$3
T
)(
T
$(
相關(guān)PDF資料
PDF描述
HYB18T512160AF-3S 512-Mbit DDR2 SDRAM
HYB18T512400AF-3 512-Mbit DDR2 SDRAM
HYB18T512400AF-3S 512-Mbit DDR2 SDRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB18T512161BF-25 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA
HYB18T512400AF-5 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA
HYB18T512400BF-3S 制造商:Qimonda 功能描述:
HYB18T512800AF-3S 制造商:Qimonda 功能描述: 制造商:Infineon Technologies AG 功能描述:32M X 16 DDR DRAM, 0.45 ns, PBGA84
HYB18T512800BF-2.5 功能描述:IC DDR2 SDRAM 512MBIT 60TFBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標準包裝:60 系列:- 格式 - 存儲器:EEPROMs - 串行 存儲器類型:EEPROM 存儲容量:16K (2K x 8) 速度:2MHz 接口:SPI 3 線串行 電源電壓:2.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-DIP（0.300"，7.62mm） 供應商設(shè)備封裝:8-PDIP 包裝:管件 產(chǎn)品目錄頁面:1449 (CN2011-ZH PDF)
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