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參數(shù)資料
| 型號： | HTG2150 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit 320 Pixel LCD Microcontroller |
| 中文描述： | 8位微控制器320像素LCD |
| 文件頁數(shù)： | 9/49頁 |
| 文件大?。?/td> | 316K |
| 代理商： | HTG2150 |
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HTG2150
9
July 24, 2000
Preliminary
Instruction(s)
Table Location
*13 *12 *11 *10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
#5
#4
#3
#2
#1
#0
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: @7~@0: TBLP register bit 7~bit 0
#5~#0: TBHP register bit 13~bit 8
*13~*0: Current Program ROM table
address bit 13~bit 0
Location 010H/014H
This area is reserved for the timer 2/3 interrupt
service program. If a timer interrupt results
fromatimer2/3overflow,andiftheinterruptis
enabled and the stack is not full, the program
begins execution at location 010H/014H.
Location 018H
This area is reserved for the D/A buffer empty
interrupt service program. After the system
latch a D/A code at RAM address 28H, the in-
terrupt is enable, and the stack is not full, the
program begins execution at location 020H.
Location 020H
For best condition, this is the starting loca-
tion for writing the program..
ROM Bank 1 (BP5~BP7=001B)
The range of the ROM starts from 2000H to
3FFFH.
Table location
Any location in the ROM space can be used as
look up tables. The instructions TABRDC [m]
(use for any bank) and TABRDL [m] (only
used for last page of program ROM) transfers
the contents of the lower-order byte to the
specified data memory, and the higher-order
byte to TBLH (08H). Only the destination of
the lower-order byte in the table is
well-defined. The higher-order byte of the ta-
ble word are transferred to the TBLH. The ta-
ble higher-order byte register (TBLH) is read
only. The table pointer (TBHP, TBLP) is a
read/write register (1FH, 07H), which indi-
cates the table location. Before accessing the
table, the location must be placed in TBLP.
The TBLH is read only and cannot be re-
stored. If the main routine and the ISR (Inter-
rupt Service Routine) both employ the table
read instruction, the contents of the TBLH in
the main routine are likely to be changed by
the table read instruction used in the ISR. Er-
rors can occur. In other words, using the table
read instruction in the main routine and the
ISR simultaneously should be avoided. How-
ever, if the table read instruction has to be ap-
plied in both the main routine and the ISR,
the interrupt is supposed to be disabled prior
to the table read instruction. It will not be en-
abled until the TBLH has been backed up. All
table related instructions need two cycles to
complete the operation. These areas may
function as normal program memory depend-
ing upon the requirements.
Stack register
STACK
This is a special part of the memory which is
used to save the contents of the program coun-
ter (PC) only. The stack is organized into eight
levels and is neither part of the data nor part of
the program space, and is neither readable nor
writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt ac-
knowledgment, the contents of the program
counter and ROM address A13 bit latch Data
are pushed onto the stack. At the end of a sub-
routine or an interrupt routine, signaled by a
return instruction (RET or RETI), the program
counter and ROM address A13 bit latch Data
are restored to its previous value from the
stack. After a chip reset, the SPwill point to the
top of the stack.
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag will be re-
cordedbuttheacknowledgmentwillbeinhibited.
When the stack pointer is decremented (by RET
or RETI), the interrupt will be serviced. This fea-
ture prevents stack overflow allowing the pro-
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