HTG2150
10
July 24, 2000
Preliminary
grammer to use the structure more easily. In a
similar case, if the stack is full and a CALL is
subsequentlyexecuted,stackoverflowoccursand
the first entry will be lost (only the most recent
eight return address are stored).
Data memory
RAM
Bank 0 (BP4~BP0=00000)
The Bank 0 data memory includes special
purpose and general purpose memory. The
special purpose memory is addressed from
00H to 2FH, while general purpose memory is
addressed from 40H to FFH. All data memory
areascanhandlearithmetic,logic,increment,
decrement and rotate operations directly. Ex-
cept for some dedicated bits, each bit in the
data memory can be set and reset by the SET
[m].i and CLR [m].i instructions, respectively.
They are also indirectly accessible through the
memorypointerregisters(MP0;01H,MP1;03H).
Bank 15 (BP4~BP0=01111B)
The range of RAM starts from 80H to A7H.
On the LCD, every bit stands for one dot. If
the bit is 1 , the light of the dot on the LCD
will be turned on. If the bit is 0 , then it will
be turned off. Only MP1 can deal with the
memory of this range.
The contrast form of RAM location, COM-
MON, and SEGMENT is as follows.
Indirectaddressingregister
Location 00H and 02H are indirect addressing
registers that are not physically implemented.
Any read/write operation of [00H] and [02H] ac-
cess data memory are pointed to by MP0 (01H)
and MP1 (03H) respectively. Reading location
00H or 02H indirectly will return the result 00H.
Writing indirectly results in no operation.
Thefunctionofdatamovementbetweentwoindi-
rect addressing registers, is not supported. The
memory pointer registers, MP0 and MP1, are
8-bit registers which can be used to access the
data memory by combining corresponding indi-
rect addressing registers but Bank 15 can use
MP1 only.
Accumulator
The accumulator is closely related to ALU oper-
ations. It is also mapped to location 05H of the
data memory and it can carry out immediate
data operations. The data movement between
two data memories has to pass through the ac-
cumulator.
2 5
+ ! 5
2 2 5
.
.
5
8 5
3
3
B# %
" 5
" 5
" 2 5
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. . 5
. 5
. + 5
. / 5
. , 5
. 5
. 4 5
. 9 5
. # 5
. 8 5
. 5
. 5
. 5
. 2 5
! 5
%
% * *
* * # *
* * C ! ! C
8 * - " ! * D !
E *
4 ! 5
# 5
8 @ * " / ** $
; + ! * 8 $ =
7 *
8 @ * ! ** $
; " 9 . * 8 $ =
! ! 5
! " 5
! . 5
! 5
! + 5
! / 5
! , 5
! 5
! 4 5
! 9 5
! # 5
! 8 5
! 5
! 5
! 5
! 2 5
" ! 5
" " 5
" . 5
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" + 5
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" , 5
" 5
" 4 5
" 9 5
" # 5
" 8 5
" 5
#
!
!
#
"
"
8
#
%
8 %
8 % 5
3
#
! 5
! %
!
#
#
8
8
# **
# * *
8 **
8 * *
* #
$ *
* #
$ *
8 @ *
#
7
* % F : - $ *
- 7 * F : 8 $ *
- 7 * 5 & : 8 $ *
3 & **
*
* *
* ! * 5 & : 8 $ *
* ! * % F : 8 $ *
* ! * *
7 *
* $
* * 5 & : 8 $ *
- 7 * & : 8 $ *
* . *
* . * *
* *
* * *
B7 * 2 * 7 7 * 7
3
*
3
*
RAM mapping