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參數(shù)資料
| 型號(hào)： | HTG2150 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 8-Bit 320 Pixel LCD Microcontroller |
| 中文描述： | 8位微控制器320像素LCD |
| 文件頁數(shù)： | 16/49頁 |
| 文件大?。?/td> | 316K |
| 代理商： | HTG2150 |
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HTG2150
16
July 24, 2000
Preliminary
4 : -
3
* 7
: -
4 :: " *
3
* :
3 ! 0 3 .
3
Watchdog Timer
There is another oscillator circuit designed for
the real time clock. In this case, only the
32768Hz crystal can be applied. The crystal
should be connected between XIN and XOUT,
and two external capacitors are required for the
oscillator circuit in order to get a stable fre-
quency.
The RTC oscillator is used to provide clock
source for the LCD driver and Timer 3. It can be
enabled or disabled by mask option.
The WDT oscillator is a free running on-chip
RC oscillator, requiring no external compo-
nents. Even if the system enters the power
down mode, and the system clock is stopped,
the WDT oscillator still runs with a period of
approximately 78 s. The WDT oscillator can be
disabled by mask option to conserve power.
Watchdog Timer
WDT
The WDT clock source is implemented by a dedi-
cated RC oscillator (WDT oscillator). This timer
is designed to prevent a software malfunction or
sequence jumping to an unknown location with
unpredictable results. The Watchdog Timer can
be disabled by mask option. If the Watchdog
Timer is disabled, all the executions related to
WDT result in no operation.
When the internal WDT oscillator (RC oscilla-
tor with 83 s period normally) is enable, it is
firstdividedby256(8stages)togetthenominal
time-out period of approximately 21ms. This
time-out period may vary with temperature,
V
DD
and process variations. By invoking the
WDT prescaler, longer time-out periods can be
realized. Writing data to WS2, WS1, WS0 (bits
2,1,0 of the WDTS) can give different time-out
periods. If WS2, WS1, WS0 are all equal to 1,
the division ratio is up to 1:128, and the maxi-
mum time-out period is 2.6 seconds.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS register
The WDT overflow under normal operation will
initialize chip reset and set the status bit TO.
Whereas in the HALT mode, the overflow will
initializea warmreset onlythePCandSPare
reset to zero. To clear the WDT contents (in-
cluding the WDT prescaler), three methods are
adopted; external reset (a low level to RES),
software instructions, or a HALT instruction.
The software instruction is CLR WDT , execu-
tion of the CLR WDT instruction will clear the
WDT.
Power down operation
HALT
The HALT mode is initialized by the HALT in-
struction and results in the following...
The system oscillator will turn off but the
WDT oscillator keeps running (if the WDT os-
cillator is selected).
The contents of the on-chip RAM and regis-
ters remain unchanged.
WDTandWDTprescalerwillbeclearedanddo
recounting again.
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