
HTG2150
23
July 24, 2000
Preliminary
Input/output ports
There are 12 bidirectional input/output lines in
the HTG2150, labeled PA and PB, which are
mapped to the data memory of [12H], [14H], re-
spectively. All these I/O ports can be used for in-
put and output operations. For input operation,
these ports are non-latching, that is, the inputs
must be ready at the T2 rising edge of instruc-
tion MOV A,[m] (m=12H, 14H). For output op-
eration, all data is latched and remains
unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC,
PBC) to control the input/output configuration.
With this control register, CMOS output or
schmitt trigger input with or without pull-high
resistor (mask option) structures can be recon-
figured dynamically under software control. To
function as an input, the corresponding latch of
the control register must write
pull-high resistance will exhibit automatically
if the pull-high option is selected. The input
source also depends on the control register. If
the control register bit is 1 , the input will read
the pad state. If the control register bit is 0 ,
the contents of the latches will move to the in-
ternal bus. The latter is possible in
read-modify-write
instruction. For output
function, CMOS is the only configuration.
These control registers are mapped to locations
13H, 15H.
1 . The
After a chip reset, these input/output lines stay
at high levels or floating (mask option). Each
bit of these input/output latches can be set or
cleared by the SET [m].i or CLR [m].i (m=12H,
14H) instruction.
Some instructions first input data and then fol-
low the output operations. For example, the
SET [m].i, CLR [m].i, CPL [m] and CPLA [m]
instructions read the entire port states into the
CPU, execute the defined operations
(bit-operation), and then write the results back
to the latches or the accumulator.
Each line of port Ahas the capability to wake-up
the device. Port B are share pad, each pin func-
tion are defined by mask option, the PB7 shares
with SEG36. The PB6, PB5 and PB4 share with
SEG35, SEG34 and SEG33. If the segment out-
put is selected, the related I/O register (PB) can-
not be used as general purpose register. Reading
the register will result to an unknown state.
PWM interface
The HTG2150 provides an 8 bit (bit 7 is a sign
bit) PWM D/A interface, which is good for
speech synthesis. The user can record or syn-
thesize the sound and digitize it into the pro-
gram ROM. These sound could be played back
in sequence of the functions as designed by the
internal program ROM. There are several algo-
rithms that can be used in the HTG2150, they
are ... PCM, LAW, DPCM, ADPCM..... .
H
(
H
(
H
# # * 8
3* *
& *
* *
3
*
*
$ * 3
@ : * ; # * 7 $ =
3 # (
7 7 :
# ! 0 #
8 + 0 8
@ *
@ *
H
Input/output ports