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參數(shù)資料
| 型號： | HT82A832R |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Basic USB Phone OTP MCU |
| 中文描述： | 檢察官辦公室的基本USB電話單片機 |
| 文件頁數(shù)： | 8/51頁 |
| 文件大?。?/td> | 345K |
| 代理商： | HT82A832R |
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HT82A832R
Rev. 1.00
8
July 18, 2006
Only the destination of the lower-order byte in the table is
well-defined, the other bits of the table word are
transferred to the lower portion of TBLH, and the
remaining 1-bit words are read as
Higher-order byte register (TBLH) is read only. The table
pointer (TBLP, TBHP) is a read/write register (07H, 1FH),
which indicates the table location. Before accessing the
table, the location must be placed in the TBLP and TBHP
registers. (If the configuration option TBHP is disabled,
the value in TBHP has no effect). TBLH is read only and
cannot be restored. If the main routine and the ISR
(Interrupt Service Routine) both employ the table read
instruction, the contents of the TBLH in the main routine
is likely to be changed by the table read instruction used
in the ISR. As a result errors may occur. In other words,
using the table read instruction in the main routine and in
the ISR simultaneously should be avoided. However, if
the table read instruction has to be applied in both the
main routine and the ISR, the interrupt should be
disabled prior to the table read instruction.
0 . The Table
It will not be enabled until the TBLH has been backed
up. All table related instructions require two cycles to
complete the operation. These areas may function as
normal program memory depending on the
requirements.
Once the TBHP is enabled, the instruction TABRDC
[m] reads the ROM data as defined by the TBLP and
TBHP register value. Otherwise, if the configuration
option TBHP is disabled, the instruction TABRDC [m]
reads the ROM data as defined by TBLPand the current
program counter bits.
Stack Register
STACK
This is a special part of the memory which is used to
save the contents of the program counter only. The
stackisorganizedinto16levelsandisneitherpartofthe
data nor part of the program space, and is neither
readable nor writeable. The activated level is indexed by
the stack pointer (SP) and is neither readable nor
writeable. At a subroutine call or interrupt acknowledge
signal, the contents of the program counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction (RET or RETI),
the program counter is restored to its previous value
from the stack. After a chip reset, the stack pointer will
point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow
allowing the programmer to use the structure more
easily. In a similar case, if the stack is full and a CALL
is subsequently executed, stack overflow occurs and
the first entry will be lost (only the most recent 16 return
addresses are stored).
Data Memory
RAM
The data memory is divided into two functional groups:
namely; special function registers and general purpose
data memory, Bank 0: 192 8 bits. Most are read/write,
but some are read only.
The special function registers include the indirect
addressing registers (R0;00H, R1;02H), Bank register
(BP;04H), Timer/Event Counter 0 higher order byte
register (TMR0H;0CH), Timer/Event Counter 0 lower
order byte register (TMR0L;0DH), Timer/Event Counter
0 control register (TMR0C;0EH), Timer/Event Counter 1
higher order byte register (TMR1H;0FH), Timer/Event
Counter 1 lower order byte register (TMR1L;10H),
Timer/Event Counter 1 control register (TMR1C;11H),
program counter lower-order byte register (PCL;06H),
memory pointer registers (MP0;01H, MP1;03H),
accumulator (ACC;05H), table pointer (TBLP;07H,
TBHP;1FH), table higher-order byte register
(TBLH;08H), status register (STATUS;0AH), interrupt
control register0 (INTC0;0BH), Watchdog Timer option
setting register (WDTS;09H), I/O registers (PA;12H,
PB;14H, PC;16H), I/O control registers (PAC;13H,
PBC;15H, PCC;17H). Digital Volume Control Register
(USVC;1CH).
USB status and control register (USC;20H), USB
endpoint interrupt status register (USR;21H), system
clock control register (UCC;22H). Address and remote
wakeup register (AWR;23H), STALL register (24H),
SIES register (25H), MISC register (26H), SETIO
register (27H). FIFO0~FIFO4 register (28H~2CH).
DAC_Limit_L register (2DH), DAC_Limit_H register
(2EH), DAC_WR register (2FH). PGA_CTRL register
(30H). PFD control register (PFDC;31H). PFD data
register (PFDD;32H). MODE_CTRL register (34H).
Serial bus control register (SBCR;35H), serial bus data
register (SBDR;36H). Play data left channel
(PLAY_DATAL_L;3AH, PLAY_DATAL_H;3BH), play
data right channel (PLAY_DATAR_L;3CH, PLAY_
DATAR_H;3DH). Record data (RECORD_DATA_L;
3EH, RECORD_DATA_H; 3FH).
The remaining space before the 40H is reserved for
future expanded usage, reading these locations will
return a result of
memory, addressed from 40H to FFH, is used for data
and control information under instruction commands.
00H . The general purpose data
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations
directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by SET [m].i and
CLR [m].i . They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HT82A832R_07 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
| HT82A834R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
| HT82A836R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
| HT82A850R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Audio MCU |
| HT82A851R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
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