
HT82A832R
Rev. 1.00
29
July 18, 2006
Mode Control
The MODE_CTRL register is used to control DAC and ADC operation mode and SPI function.
Bit No.
Label
Functions
0
DA_L_ENB
DAC enable/disable control (left channel)
1= DAC Left Channel disable
0= DAC Left Channel enable (default)
1
DA_R_ENB
DAC enable/disable control (right channel)
1= DAC Right Channel disable
0= DAC Right Channel enable (default)
2
AD_ENB
ADC enable/disable control
1= ADC power down
0= ADC power on (default)
3
PLAY_MODE
DAC play mode control
1= 8kHz/16-bit
0= 48kHz/16-bit (default)
4
SIO_CPOL
There are three bits used to control the mode of SPI operation.
1= clock polarity rising edge
0= clock polarity falling edge (default)
5
SIO_WCOL
1= WCOL bit of SBCR register enable
0= WCOL bit of SBCR register disable (default)
6
SIO_CSEN
1= CSEN bit of SBCR register enable
0= CSEN bit of SBCR register disable (Default)
7
Undefined bit, read as 0
MODE_CTRL (34H) Register
SPI Usage Example
SPI_Test:
clr
set
clr
;Master Mode, SCLK=fSIO
clr
M1
clr
M0
;--------------
clr
CKS
clr
TRF
clr
TRF_INT
set
MLS
set
CSEN
set
SBEN
if POLLING_MODE
clr
ESII
;WRITE INTO "WRITE ENABLE" INSTRUCTION
MOV
A,OP_WREN
MOV
SBDR,A
$0:
snz
TRF
jmp
$0
clr
TRF
else
set
ESII
;WRITE INTO "WRITE ENABLE" INSTRUCTION
MOV
A,OP_WREN
MOV
SBDR,A
$0:
snz
TRF_INT
jmp
$0
clr
TRF_INT
endif
UCC.@UCC_SYSCLK
SIO_CSEN
SIO_CPOL
;12MHz SYSCLK
;SPI Chip Select Function Enable
;falling edge change data
;fSIO=fsys/2
;clear TRF flag
;clear Interrupt SPI flag
;MSB shift first
;Chip Select Enable
;SPI Enable, SCS will go low
;SPI Interrupt Disable
;SPI Interrupt Enable
;set at SPI Interrupt