參數(shù)資料
型號(hào)： HT82A832R
廠商： Holtek Semiconductor Inc.
英文描述： Basic USB Phone OTP MCU
中文描述： 檢察官辦公室的基本USB電話單片機(jī)
文件頁(yè)數(shù)： 26/51頁(yè)
文件大?。?/td> 345K
代理商： HT82A832R
HT82A832R
Rev. 1.00
26
July 18, 2006
Disable: SCK (SCK), SDI, SDO, SCS floating and related pins are IO ports.
Label
Functions
SBEN=1
PC4~PC7 are SPI function pins (pin SCS will go low if CSEN=1).
SBEN=0
PC4~PC7 are general purpose I/O Port pins (Default)
Note: 1. If SBEN= 1 , the pull-high resistors on PC4~PC7 will be disabled. When this happens the user should
add external pull-high resistors to the SPI related pins if necessary (EX: pin SCS).
2. If CSEN= 0 , the SCS pin will enter a floating state.
Bit3 (MLS): MSB or LSB (1/0) shift first control bit
Bit2 (CSEN): serial bus selection signal enable/disable (SCS), when CSEN=0, SCS is floating
Bit1 (WCOL): this bit is set to 1 if data is written to SBDR (TXRX buffer) when a data is transferring
writing will be ignored if data is written to SBDR (TXRX buffer) when a data is transferring
WCOL will be set by hardware and clear by software.
Bit 0 (TRF): data transferred or data received
Note: data receiving is still working when MCU enters halt mode
used to generate interrupt
SBDR: Serial bus data register
Data written to SBDR
Data read from SBDR
write data to TXRX buffer only
read from SBDR only
Operating Mode description:
Master transmitter: clock sending and data I/O started by writing SBDR
Master clock sending started by writing SBDR
Slave transmitter: data I/O started by clock received
Slave receiver: data I/O started by clock received
Clock polarity = rising (CLK) or falling (CLK): 1 or 0 (software option)
Operation of Serial Interface:
Label
Functions
Master
Select CKS and select M1,M0 = 00, 01, 10
Select CSEN, MLS (same as slave)
Set SBEN
Writing data to SBDR
step 5
(SIO internal operation
TXRX buffer
data transferred, data in TXRX buffer is latched into SBDR)
Check WCOL; WCOL = 1
clear WCOL and go to step 4; WCOL = 0
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
data is stored in TXRX buffer
data stored in TXRX buffer, and SDI data is shifted into
output CLK (and SCS) signals
go to
go to step 6
Slave
CKS don t care and select M1, M0 = 11
Select CSEN, MLS (same as master)
Set SBEN
Writing data to SBDR
SCS): CLK
go to step 5
TXRX buffer and SDI data is shifted into TXRX buffer
latched into SBDR)
Check WCOL; WCOL = 1
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
data is store in TXRX buffer
(SIO internal operations
waiting for master clock signal (and
CLK (SCS) received
data transferred, data in TXRX buffer is
output data in
clear WCOL, go to step 4; WCOL = 0
go to step 6
WCOL:master/slavemode,setifwritingtoSBDRwhendataistransferring(transmittingorreceiving)andthiswriting
will be ignored. WCOL function can be enabled/disabled by software option (SIO_WCOL bit of MODE_CTRL regis-
ter). WCOL is set by SIO and cleared by users.
Data transmission and reception are still workable when MCU enters halt mode.
CPOL is used to select the clock polarity of CLK. It is a software option (SIO_CPOL bit of MODE_CTRL register).
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