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參數(shù)資料
| 型號： | HT82A832R |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Basic USB Phone OTP MCU |
| 中文描述： | 檢察官辦公室的基本USB電話單片機 |
| 文件頁數(shù)： | 10/51頁 |
| 文件大小： | 345K |
| 代理商： | HT82A832R |
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HT82A832R
Rev. 1.00
10
July 18, 2006
In addition, upon entering the interrupt sequence or
executing a subroutine call, the status register will not
be automatically pushed onto the stack. If the contents
of the status are important and if the subroutine can
corrupt the status register, precautions must be taken to
save it properly.
Interrupt
The device provides a USB interrupt, internal
timer/event counter interrupts, play/record data valid
interrupt and a serial interface interrupt. The Interrupt
Control Register0 (INTC0;0BH) and interrupt control
register1 (INTC1;1EH) both contain the interrupt control
bits that are used to set the enable/disable status and
interrupt request flags.
Once an interrupt subroutine is serviced, all the other
interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain
interrupt requires servicing within the service routine,
the EMI bit and the corresponding bit of the INTC0 or
INTC1 may be set to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the stack
pointer is decremented. If immediate service is desired,
the stack must be prevented from becoming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register (STATUS) are altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
The USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC0) will be set.
Accessing the corresponding USBFIFO from the PC
The USBsuspend signal from the PC
The USBresume signal from the PC
USB Reset signal
When the interrupt is enabled, the stack is not full and
the USB interrupt is active, a subroutine call to location
04H will occur. The interrupt request flag (USBF) and
EMI bits will be cleared to disable other interrupts.
When the PC Host accesses the FIFO of the
HT82A832R, the corresponding request bit of the USR
is set, and a USB interrupt is triggered. So the user can
easily determine which FIFO has been accessed. When
the interrupt has been served, the corresponding bit
should be cleared by firmware. When the HT82A832R
receives a USB Suspend signal from the Host PC, the
suspend line (bit0 of USC) of the HT82A832R is set and
a USB interrupt is also triggered.
Also when the HT82A832R receives a Resume signal
from the Host PC, the resume line (bit3 of USC) of the
HT82A832R is set and a USB interrupt is triggered.
The internal Timer/Event Counter 0 interrupt is
initialized by setting the Timer/Event Counter 0 interrupt
request flag (bit 5 of INTC0), caused by a timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further
interrupts.
The internal Timer/Event counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (bit 6 of INTC0), caused by a timer 1 overflow. When
the interrupt is enabled, the stack is not full and T1F is
set, a subroutine call to location 0CH will occur. The
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
takeplaceduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by
executing the HALT instruction.
5
TO
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is
set by a WDT time-out.
6~7
Unused bit, read as 0
Status (0AH) Register
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相關代理商/技術(shù)參數(shù) |
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| HT82A832R_07 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
| HT82A834R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
| HT82A836R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
| HT82A850R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Audio MCU |
| HT82A851R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
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