HT82A832R
Rev. 1.00
19
July 18, 2006
Bit No.
Label
R/W
Reset
Functions
0
SUSP
R
0
Read only, USB suspend indication. When this bit is set to 1 (set
by SIE), it indicates that the USB bus has entered the suspend
mode. The USB interrupt is also triggered when this bit changes
from low to high.
1
RMWK
R/W
0
USB remote wake-up command. It is set by MCU to force the USB
host to leave the suspend mode.
2
URST
R/W
0
USB reset indication. This bit is set/cleared by the USB SIE. This bit
is used to detect a USB reset event on the USB bus. When this bit is
set to 1 , this indicates that a USB reset has occurred and that a
USB interrupt will be initialized.
3
RESUME
R
0
USB resume indication. When the USB leaves the suspend mode,
this bit is set to 1 (set by SIE). When the RESUME is set by SIE, an
interrupt will be generated to wake-up the MCU. In order to detect
the suspend state, the MCU should set USBCKEN and clear
SUSP2 (in the UCC register) to enable the SIE detect function.
RESUME will be cleared when the SUSP goes to 0 . When the
MCU is detecting the SUSP, the condition of RESUME (causes the
MCU to wake-up) should be noted and taken into consideration.
4
V33C
R/W
0
0/1: Turn-off/on V33O output
5~6
Undefined bit, read as 0 .
7
URD
R/W
1
USB reset signal control function definition
1: USB reset signal will reset MCU
0: USB reset signal cannot reset MCU
USC (20H) Register
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select
the serial bus (USB). The endpoint request flags (EP0F, EP1F, EP2F, EP3F, EP4F) are used to indicate which end-
points are accessed. If an endpoint is accessed, the related endpoint request flag will be set to 1 and the USB inter-
rupt will occur (if the USB interrupt is enabled and the stack is not full). When the active endpoint request flag is
serviced, the endpoint request flag has to be cleared to 0 by software.
Bit No.
Label
R/W
Reset
Functions
0
EP0F
R/W
0
When this bit is set to 1 (set by SIE), it indicates that endpoint 0
has been accessed and a USB interrupt will occur. When the
interrupt has been serviced, this bit should be cleared by software.
1
EP1F
R/W
0
When this bit is set to 1 (set by SIE), it indicates that endpoint 1
has been accessed and a USB interrupt will occur. When the
interrupt has been serviced, this bit should be cleared by software.
2
EP2F
R/W
0
When this bit is set to 1 (set by SIE), it indicates that endpoint 2
has been accessed and a USB interrupt will occur. When the
interrupt has been serviced, this bit should be cleared by software.
3
EP3F
R/W
0
When this bit is set to 1 (set by SIE), it indicates that endpoint 3
has been accessed and a USB interrupt will occur. When the
interrupt has been serviced, this bit should be cleared by software.
4
EP4F
R/W
0
When this bit is set to 1 (set by SIE), it indicates that endpoint 4
has been accessed and a USB interrupt will occur. When the
interrupt has been serviced, this bit should be cleared by software.
5~7
Undefined bit, read as 0 .
USR (21H) Register