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參數(shù)資料
| 型號： | HT82A832R |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | Basic USB Phone OTP MCU |
| 中文描述： | 檢察官辦公室的基本USB電話單片機(jī) |
| 文件頁數(shù)： | 13/51頁 |
| 文件大?。?/td> | 345K |
| 代理商： | HT82A832R |
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HT82A832R
Rev. 1.00
13
July 18, 2006
CLR WDT and the other set CLR WDT1 and CLR
WDT2 . Of these two types of instruction, only one type
of instruction can be active at a time depending on the
configuration option CLR WDT times selection option.
If the CLR WDT is selected (i.e., CLR WDT times
equal one), any execution of the CLR WDT instruction
clears the WDT. In the case that CLR WDT1 and CLR
WDT2 are chosen (i.e., CLR WDT times equal two),
these two instructions have to be executed to clear the
WDT; otherwise, the WDT may reset the chip due to a
time-out.
Power Down Operation
HALT
The HALT mode is initialized by the HALT instruction
and results in the following:
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
The contents of the on-chip RAM and registers remain
unchanged.
The WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
All of the I/O ports remain in their original status.
The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge
signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow
performs a warm reset . After the TO and PDF flags
are examined, the cause for chip reset can be
determined. The PDF flag is cleared by a system
power-up or executing the CLR WDT instruction and
is set when executing the HALT instruction. The TO
flag is set if a WDT time-out occurs, and causes a
wake-up that only resets the program counter and stack
pointer; the others remain in their original status.
The port A wake-up and interrupt methods can be
considered as a continuation of normal execution. Each
bit in port A can be independently selected to wake-up
the device by configuration option. Awakening from an
I/O port stimulus, the program will resume execution of
the next instruction. If it awakens from an interrupt, two
sequence may occur. If the related interrupt is disabled
or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the
regular interrupt response takes place. If an interrupt
request flag is set to 1 before entering the HALTmode,
the wake-up function of the related interrupt will be
disabled. Once a wake-up event occurs, it takes 1024
t
SYS
(system clock period) to resume normal operation.
In other words, a dummy period will be inserted after a
wake-up. If the wake-up results from an interrupt
acknowledge signal, the actual interrupt subroutine
execution will be delayed by one or more cycles. If the
wake-up results in the next instruction execution, this
will be executed immediately after the dummy period is
finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
Reset
Therearefourwaysinwhicharesetcanoccur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
USB reset
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a
warm
reset that resets only the program counter and stack
pointer, leaving the other circuits in their original state.
Some registers remain unchanged during other reset
conditions. Most registers are reset to the
initial
condition
examining the PDF and TO flags, the program can
when the reset conditions are met. By
distinguish between different chip resets .
TO
PDF
RESET Conditions
0
0
RESET reset during power-up
u
u
RESET reset during normal operation
0
1
RESET wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Note: u stands for unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the
system resets (power-up, WDT time-out or RES reset)
or the system awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will
enable the SST delay.
The functional unit chip reset status are shown below.
Program Counter
000H
Interrupt
Disable
WDT
Clear. After master reset,
WDT begins counting
Timer/event Counter
Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
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相關(guān)代理商/技術(shù)參數(shù) |
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| HT82A832R_07 | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
| HT82A834R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
| HT82A836R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
| HT82A850R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:Audio MCU |
| HT82A851R | 制造商:HOLTEK 制造商全稱:Holtek Semiconductor Inc 功能描述:USB Audio MCU |
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