參數(shù)資料
型號(hào)： HT82A832R
廠商： Holtek Semiconductor Inc.
英文描述： Basic USB Phone OTP MCU
中文描述： 檢察官辦公室的基本USB電話單片機(jī)
文件頁(yè)數(shù)： 23/51頁(yè)
文件大?。?/td> 345K
代理商： HT82A832R
HT82A832R
Rev. 1.00
23
July 18, 2006
Label
R/W
Power-on
Functions
FIFO0~
FIFO4
R/W
xxH
EPi accessing register (i = 0~4). When an endpoint is disabled, the corresponding
accessing register should be disabled.
FIFO0~4 (28H~2CH) USB Endpoint Accessing Register Definitions
DAC_Limit_Land DAC_Limit_H are used to define the 16-bit DAC output limit. DAC_Limit_Land DAC_Limit_H are un-
signedvalue.Ifthe16-bitdatafromtheHostovertherangedefinedbyDAC_Limit_LandDAC_Limit_H,theoutputdigi-
tal code to DAC will be clamped.
DAC_Limit_L
DAC output limit low byte
DAC_Limit_H
DAC output limit high byte
Example to set the DAC output limit value:
;-----------------------------------------------------------
; Set DAC Limit Value=FF00H
;-----------------------------------------------------------
clr
[02DH]
; Set DAC Limit low byte=00H
set
[02EH]
; Set DAC Limit high byte=FFH
;-----------------------------------------------------------
In order to prevent a popping noise from the speaker output, the power amplifier should output a value of VDD/2 (send
8000H to DAC) during the initial power on state. If the software is set high then clear the bit DAC_WR_TRIG (bit 3 of
DAC_WR register), the value on the DAC_Limit_L and DAC_Limit_H registers will write to the DAC.
Bit No.
Label
R/W
Power-on
Functions
0~2, 4~7
R
0
Undefined bit, read as 0 .
3
DAC_WR_TRIG
R/W
0
DAC write trigger bit
DAC_WR (2FH) Register
Example to avoid popping noise:
System_Initial:
;-----------------------------------------------------------
; Avoid Pop Noise
;-----------------------------------------------------------
mov
a,WDTS
mov
FIFO_TEMP,a
mov
a,00001111b
andm
a,WDTS
mov
a,01010000b
orm
a,WDTS
clr
[02DH]
mov
a,80H
mov
[02EH],a
nop
;Write 8000H to DAC
set
[02FH].3
nop
clr
[02FH].3
nop
;-----------------------------------------------------------
mov
a,FIFO_TEMP
mov
WDTS,a
;-----------------------------------------------------------
;Save WDTS value
;Enter DAC Write Data mode, high nibble of WDTS=0101b
;Set DAC data low byte=00H
;Set DAC data high byte=80H
;Restore WDTS value
;Quit DAC Write Data mode
Note: At DAC write data mode (high nibble of WDTS register is 0101b), DAC_Limit_Land DAC_Limit_H registers will
be the 16-bit DAC input data register at falling edge of DAC_WR_TRIG. Otherwise, these two registers are
used to define the 16-bit DAC output limit.
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相關(guān)代理商/技術(shù)參數(shù)
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