參數(shù)資料
型號： HT82A832R
廠商： Holtek Semiconductor Inc.
英文描述： Basic USB Phone OTP MCU
中文描述： 檢察官辦公室的基本USB電話單片機
文件頁數(shù)： 12/51頁
文件大?。?/td> 345K
代理商： HT82A832R
HT82A832R
Rev. 1.00
12
July 18, 2006
Oscillator Configuration
The microcontroller contains an integrated oscillator
circuit.
This oscillator is designed for the system clock. The
HALT mode stops the system oscillator and ignores any
external signals to conserve power.
A crystal across OSCI and OSCO is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. If preferred,
a resonator can also be connected between OSCI and
OSCO for oscillation to occur, but two external
capacitors connected between OSCI, OSCO and
ground are required.
The WDT oscillator is a free running on-chip RC
oscillator, and no external components are required.
Even if the system enters the power down mode, the
system clock stops running, but the WDT oscillator still
continues to run. The WDT oscillator can be disabled by
a configuration option to conserve power.
Watchdog Timer
WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or the instruction clock
(system clock/4). The timer is designed to prevent a
software malfunction or sequence from jumping to an
unknown location with unpredictable results. The WDT
can be disabled by a configuration option. However, if
the WDT is disabled, all executions related to the WDT
lead to no operation.
When the WDT clock source is selected, it will be first
divided by 256 (8-stage) to get the nominal time-out
period. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 can give different time-out periods.
The WDT OSC period is typically 65 s. This time-out
period may vary with temperature, VDD and process
variations. The WDT OSC always keeps running in any
operation mode.
If the instruction clock is selected as the WDT clock
source,theWDToperatesinthesamemannerexceptin
the halt mode. In the HALT mode, the WDT stops
counting and lose its protecting purpose. In this situation
the logic can only be re-started by external logic. The
high nibble of the WDTS is reserved for the DAC write
mode.
The WDT overflow under normal operation initializes a
chip reset and sets the status bit TO . In the HALT
mode, the overflow initializes a warm reset , and only
the program counter and stack pointer are reset to zero.
To clear the contents of the WDT, there are three
methods to be adopted, i.e., an external reset (a low
level to RESET), a software instruction, and a HALT
instruction. There are two types of software instructions;
& %
& &
System Oscillator
%
&
B ( 0
9 :
%
%
&
+ 9 :
%
9
9 %
%
9
) *
1
B
&
%
Watchdog Timer
Bit No.
Label
Function
0
1
2
WS0
WS1
WS2
Watchdog Timer division ratio selection bits
Bit 2,1,0 = 000, Division Ratio = 1:1
Bit 2,1,0 = 001, Division Ratio = 1:2
Bit 2,1,0 = 010, Division Ratio = 1:4
Bit 2,1,0 = 011, Division Ratio = 1:8
Bit 2,1,0 = 100, Division Ratio = 1:16
Bit 2,1,0 = 101, Division Ratio = 1:32
Bit 2,1,0 = 110, Division Ratio = 1:64
Bit 2,1,0 = 111, Division Ratio = 1:128
3
Unused bit, read as 0
7~4
T3~T0
Test mode setting bits
(T3,T2,T1,T0) = (0,1,0,1), enter DAC write mode. Otherwise normal operation.
WDTS (09H) Register
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