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參數(shù)資料
| 型號： | HT48E50 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | I/O Type 8-Bit MTP MCU With EEPROM |
| 中文描述： | I / O型8位微控制器帶有EEPROM中期計劃 |
| 文件頁數(shù)： | 8/46頁 |
| 文件大小： | 303K |
| 代理商： | HT48E50 |
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HT48E50
Rev. 0.00
8
September 29, 2004
Preliminary
In System Programming
In system programming allows programming and repro-
gramming of HT48EXX microcontroller on application
circuit board, this will save time and money, both during
development in the lab. Using a simple 3-wire interface,
the ISP communicates serially with the HT48EXX
microcontroller, reprogramming program memory and
EEPROM data memory on the chip.
Pin Name Function
Description
PA0
SDATA
Serial data input/output
PA4
SCLK
Serial clock input
RES
RESET
Device reset
VDD
VDD
Power supply
VSS
VSS
Ground
ISP Pin Assignments
Program Memory
ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096 15bits,addressedbytheprogramcounterandta-
ble pointer.
Certain locations in the program memory are reserved
for special usage:
Location 000H
This area is reserved for program initialization. After a
chip reset, the program always begins execution at lo-
cation 000H.
Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabledand the stack is not full, the program begins
execution at location 004H.
Location 008H
This area is reserved for the Timer/Event Counter 0 in-
terruptserviceprogram.Ifatimerinterruptresultsfroma
Timer/Event Counter 0 overflow, and if the interrupt is
enabled and the stack is not full, the program begins ex-
ecution at location 008H.
Location 00CH
This location is reserved for the Timer/Event Counter
1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the inter-
rupt is enabled and the stack is not full, the program
begins execution at location 00CH.
Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m] (the
current page, one page=256 words) and TABRDL
[m]
lower-order byte to the specified data memory, and
the higher-order byte to TBLH (08H). Only the desti-
nation of the lower-order byte in the table is
well-defined, the other bits of the table word are trans-
ferred to the lower portion of TBLH, and the remaining
(the last page) transfer the contents of the
1-bit words are read as 0 . The Table Higher-order
byte register (TBLH) is read only. The table pointer
(TBLP) is a read/write register (07H), which indicates
the table location. Before accessing the table, the lo-
cation must be placed in the TBLP. The TBLH is read
only and cannot be restored. If the main routine and
the ISR (Interrupt Service Routine) both employ the
table read instruction, the contents of the TBLH in the
main routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main rou-
tine and the ISR simultaneously should be avoided.
However, if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt is
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Program Memory
Instruction
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table pointer bits
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