參數(shù)資料
型號(hào): HT48E50
廠商: Holtek Semiconductor Inc.
英文描述: I/O Type 8-Bit MTP MCU With EEPROM
中文描述: I / O型8位微控制器帶有EEPROM中期計(jì)劃
文件頁(yè)數(shù): 10/46頁(yè)
文件大?。?/td> 303K
代理商: HT48E50
HT48E50
Rev. 0.00
10
September 29, 2004
Preliminary
eration to [00H] ([02H]) access the data memory pointed
to by MP0 (MP1). Reading location 00H (02H) itself indi-
rectly will return the result 00H. Writing indirectly results
in no operation.
The memory pointer registers (MP0 and MP1) are 8-bit
registers used to access the RAM by combining corre-
sponding indirect addressing registers.
MP0 can only be applied to data memory in Bank 0,
while MP1 can be applied to data memory in Bank 0 and
Bank 1.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Arithmetic and Logic Unit
ALU
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
Logic operations (AND, OR, XOR, CPL)
Rotation (RL, RR, RLC, RRC)
Increment and Decrement (INC, DEC)
Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but
also changes the status register.
Status Register
STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
Labels
Bits
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addi-
tion, operations related to the status register may
give different results from those intended. The TO
flag can be affected only by a system power-up, a
WDT time-out or executing the
CLR WDT
or
HALT
instruction. The PDF flag can be affected
only by executing the HALT or CLR WDT instruc-
tion or during a system power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
Interrupt
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
to enable or disable the interrupt request flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain inter-
rupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be set
to allow interrupt nesting. If the stack is full, the interrupt
request will not be acknowledged, even if the related in-
terruptisenabled,untiltheSPisdecremented.Ifimmedi-
ate service is desired, the stack must be prevented from
becoming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
Function
C
0
C is set if an operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC
1
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV
3
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the high-
est-order bit, or vice versa; otherwise OV is cleared.
PDF
4
PDFisclearedbyasystempower-uporexecutingthe CLRWDT instruction.PDFissetbyex-
ecuting the HALT instruction.
TO
5
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is
set by a WDT time-out.
6
Unused bit, read as 0
7
Unused bit, read as 0
Status Register
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