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參數(shù)資料
| 型號： | HT48E50 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | I/O Type 8-Bit MTP MCU With EEPROM |
| 中文描述： | I / O型8位微控制器帶有EEPROM中期計劃 |
| 文件頁數(shù)： | 19/46頁 |
| 文件大?。?/td> | 303K |
| 代理商： | HT48E50 |
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HT48E50
Rev. 0.00
19
September 29, 2004
Preliminary
EEPROM Data Memory
The 256 8 bits EEPROM data memory is readable and writable during normal operation. It is indirectly addressed
through the control register EECR ([40H] in Bank 1). The EECR can be read and written to only by indirect addressing
mode using MP1.
Label (EECR)
Bits
Function
0~3
Unused bit, read as 0
CS
4
EEPROM data memory select
SK
5
Serial clock input to EEPROM data memory
DI
6
Serial data input to EEPROM data memory
DO
7
Serial data output from EEPROM data memory
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EEPROM Data Memory Block Diagram
The EEPROM data memory is accessed via a
three-wire serial communication interface by writing to
EECR. It is arranged into 256 words by 8 bits. The
EEPROM data memory contains seven instructions:
READ, ERASE, WRITE, EWEN, EWDS, ERAL and
WRAL. These instructions are all made up of 12 bits
data: 1 start bit, 2 op-code bits and 9 address bits.
By writing CS, SK and DI, these instructions can be
transmitted to the EEPROM. These serial instruction
data presented at the DI will be written into the
EEPROM data memory at the rising edge of SK. During
the READ cycle, DO acts as the data output and during
the WRITE or ERASE cycle, DO indicates the
BUSY/READY status. When the DO is active for read
data or as a BUSY/ READY indicator the CS pin must be
high; otherwise DO will be in a high state. For successful
instructions, CS must be low once after the instruction is
sent. After power on, the device is by default in the
EWDS state. An EWEN instruction must be performed
before any ERASE or WRITE instruction can be exe-
cuted.
The following are the functional descriptions and timing diagrams of all seven instructions.
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相關(guān)PDF資料 |
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