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參數(shù)資料
| 型號： | HT48E50 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | I/O Type 8-Bit MTP MCU With EEPROM |
| 中文描述： | I / O型8位微控制器帶有EEPROM中期計劃 |
| 文件頁數(shù)： | 12/46頁 |
| 文件大?。?/td> | 303K |
| 代理商： | HT48E50 |
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HT48E50
Rev. 0.00
12
September 29, 2004
Preliminary
If an RC oscillator is used, an external resistor between
OSC1 and VDD is required and the resistance must
range from 24k
4, is available on OSC2, which can be used to synchro-
nize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency of oscil-
lation may vary with VDD, temperatures and the chip it-
self due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accu-
rate oscillator frequency is desired.
to 1M . The system clock, divided by
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator. No other external compo-
nents are required. In stead of a crystal, a resonator can
also be connected between OSC1 and OSC2 to get a
frequency reference, but two external capacitors in
OSC1 and OSC2 are required.
The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the sys-
tem enters the power down mode, the system clock is
stopped, but the WDT oscillator still works within a period
of 65 s at 5V. The WDT oscillator can be disabled by op-
tions to conserve power.
Watchdog Timer
WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4), determines the options. This
timer is designed to prevent a software malfunction or
sequence from jumping to an unknown location with un-
predictable results. The Watchdog Timer can be dis-
abled by options. If the Watchdog Timer is disabled, all
theexecutionsrelatedtotheWDTresultinnooperation.
Once the internal WDT oscillator (RC oscillator with a
period of 65 s at 5V normally) is selected, it is first di-
vided by 256 (8-stage) to get the nominal time-out pe-
riod of 17ms at 5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.1s at 5V
seconds. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and oper-
ates in the same manner except that in the HALT state
the WDT may stop counting and lose its protecting pur-
pose. In this situation the logic can only be restarted by
external logic. The high nibble and bit 3 of the WDTS are
reserved for user's defined flags, which can be used to
indicate some specified status.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS Register
The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO . But in the
HALT mode, the overflow will initialize a warm reset
and only the PC and SP are reset to zero. To clear the
WDT contents (including the WDT prescaler), three
methods are adopted; external reset (a low level to
RES), software instruction and a
HALT
instruction.
The software instruction include CLR WDT and the
other set
two types of instruction, only one can be active depend-
CLR WDT1 and CLR WDT2 . Of these
ing on the option
CLR WDT times selection option . If
the CLR WDT is selected (i.e. CLRWDTtimes is equal
to one), any execution of the CLR WDT instruction will
clear the WDT. In the case that CLR WDT1 and CLR
WDT2 are chosen (i.e. CLRWDTtimes is equal to two),
these two instructions must be executed to clear the
WDT; otherwise, the WDTmay reset the chip as a result
of time-out.
Power Down Operation
HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
"
+
= 0
7 ; > $ " +
! "
*
+
- ; > $ " +
! "
7 ; " ; +
*
+ $
; "
*
, *
# " $ !
"
*
Watchdog Timer
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