參數(shù)資料
型號(hào)： HT48E50
廠商： Holtek Semiconductor Inc.
英文描述： I/O Type 8-Bit MTP MCU With EEPROM
中文描述： I / O型8位微控制器帶有EEPROM中期計(jì)劃
文件頁(yè)數(shù)： 17/46頁(yè)
文件大?。?/td> 303K
代理商： HT48E50
HT48E50
Rev. 0.00
17
September 29, 2004
Preliminary
Counter 0/1 reloading will occur at the same time). When
the Timer/Event Counter 0/1 (reading TMR0/TMR1) is
read, the clock will be blocked to avoid errors. As clock
blocking may result in a counting error, this must be taken
into consideration by the programmer.
The bit0~bit2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of the
Timer/Event Counter 0. The definitions are as shown.
The overflow signal of the Timer/Event Counter 0 can be
used to generate PFD signals for buzzer driving.
Input/Output Ports
There are 33 bidirectional input/output lines in the
microcontroller, labeled from PAto PD and PG, which are
mapped to the data memory of [12H], [14H], [16H], [18H]
and [1EH] respectively. All of these I/O ports can be used
for input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready at
the T2 rising edge of instruction MOV A,[m] (m=12H,
14H, 16H, 18H or 1EH). For output operation, all the data
is latched and remains unchanged until the output latch is
rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PDC, PGC) to control the input/output configura-
tion. With this control register, CMOS output or Schmitt
trigger input with or without pull-high resistor structures
canbereconfigureddynamicallyundersoftwarecontrol.
To function as an input, the corresponding latch of the
control register must write a 1 . The input source also
depends on the control register. If the control register bit
is 1 , the input will read the pad state. If the control reg-
isterbitis 0 ,thecontentsofthelatcheswillmovetothe
internal bus. The latter is possible in the
read-modify-write instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H, 19H and 1FH.
Afterachipreset,theseinput/outputlinesremainathigh
levels or floating state (depending on the pull-high op-
tions). Each bit of these input/output latches can be set
or cleared by SET [m].i and CLR [m].i (m=12H, 14H,
16H, 18H or 1EH) instructions.
Some instructions first input data and then follow the
output operations. For example,
SET [m].i ,
CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has a capability of waking-up the de-
vice. The highest 7-bit of port G are not physically imple-
mented;onreadingthema 0 isreturnedwhereaswriting
then results in no-operation. See Application note.
There is a pull-high option available for all I/O lines (bit
option). Once the pull-high option of an I/O line is se-
lected, the I/O line have pull-high resistor. Otherwise,
the pull-high resistor is absent. It should be noted that a
non-pull-high I/O line operating in input mode will cause
a floating state.
The PB0 and PB1 are pin-shared with BZ and BZ signal,
respectively. If the BZ/BZ option is selected, the output
signal in output mode of PB0/PB1 will be the PFD signal
generated by the Timer/Event Counter 0 overflow sig-
nal. The input mode always remain in its original func-
tions. Once the BZ/BZ option is selected, the buzzer
output signals are controlled by the PB0 data register
only.
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Input/Output Ports
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