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參數(shù)資料
| 型號： | HT48E50 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | I/O Type 8-Bit MTP MCU With EEPROM |
| 中文描述： | I / O型8位微控制器帶有EEPROM中期計劃 |
| 文件頁數(shù)： | 11/46頁 |
| 文件大小： | 303K |
| 代理商： | HT48E50 |
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HT48E50
Rev. 0.00
11
September 29, 2004
Preliminary
pushing the program counter onto the stack, followed by
a branch to a subroutine at a specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register (STATUS) are altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
External interrupts are triggered by a high to low transi-
tionoftheINTandtherelatedinterruptrequestflag(EIF;
bit 4 of the INTC) will be set. When the interrupt is en-
abled, the stack is not full and the external interrupt is
active, a subroutine call to location 04H will occur. The
interrupt request flag (EIF) and EMI bits will be cleared
to disable other interrupts.
The internal Timer/Event Counter 0 interrupt is initial-
ized by setting the Timer/Event Counter 0 interrupt re-
quest flag (T0F; bit 5 of the INTC), caused by a timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further in-
terrupts.
The internal timer/event counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (;bit 6 of the INTC), caused by a timer 1 overflow.
When the interrupt is enabled, the stack is not full and
the T1F is set, a subroutine call to location 0CH will oc-
cur. The related interrupt request flag (T1F) will be reset
and the EMI bit cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledge signals are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI
may be invoked. RETI will set the EMI bit to enable an in-
terrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
No.
Interrupt Source
Priority Vector
a
External Interrupt
1
04H
b
Timer/EventCounter0Overflow
2
08H
c
Timer/EventCounter1Overflow
3
0CH
The Timer/Event Counter 0/1 interrupt request flag
(T0F/T1F), external interrupt request flag (EIF), enable
Timer/Event Counter 0/1 interrupt bit (ET0I/ET1I), en-
able external interrupt bit (EEI) and enable master inter-
rupt bit (EMI) constitute an interrupt control register
(INTC) which is located at 0BH in the data memory. EMI,
EEI, ET0I and ET1I are used to control the enabling or
disabling of interrupts. These bits prevent the requested
interrupt from beingserviced. Once the interrupt request
flags(T0F,T1F,EIF)areset,theywillremainintheINTC
register until the interrupts are serviced or cleared by a
software instruction.
It is recommended that a program does not use the
CALL subroutine within the interrupt subroutine. In-
terrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
Oscillator configuration
There are 2 oscillator circuits in the microcontroller.
All of them are designed for system clocks, namely the
external RC oscillator and the external Crystal oscillator,
which are determined by options. No matter what oscil-
lator type is selected, the signal provides the system
clock. The HALT mode stops the system oscillator and
ignores an external signal to conserve power.
Register
Bit No.
Label
Function
INTC
(0BH)
0
EMI
Controls the master (global) interrupt (1=enable; 0=disable)
1
EEI
Controls the external interrupt (1=enable; 0=disable)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enable; 0= disable)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
4
EIF
External interrupt request flag (1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
Unused bit, read as 0
INTC Register
"
+
$
"
+
$
"
+
#
! +
$ !
0
0 -
# 9
System Oscillator
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