HT48E50
Rev. 0.00
15
September 29, 2004
Preliminary
Timer/Event Counter
Two timer/event counters (TMR0, TMR1) are imple-
mented in the microcontroller. The Timer/Event Counter
0 contains an 8-bit programmable count-up counter and
the clock may come from an external source or from the
system clock.
The Timer/Event Counter 1 contains a 16-bit program-
mable count-up counter and the clock may come from
an external source or from the system clock divided by
4.
Using an external clock input allows the user to count
external events, measure time internals or pulse widths,
or generate an accurate time base. While using the in-
ternalclockallowstheusertogenerateanaccuratetime
base.
The Timer/Event Counter 0 can generate PFD signal by
using external or internal clock and the PFD frequency
is determine by the equation f
INT
/[2 (256-N)].
There are 2 registers related to the Timer/Event Counter
0; TMR0 ([0DH]), TMR0C ([0EH]). Two physical regis-
ters are mapped to TMR0 location; writing to TMR0
makes the starting value be placed in the Timer/Event
Counter 0 preload register and reading TMR0 retrieves
the contents of the Timer/Event Counter 0. The TMR0C
is a timer/event counter control register, which defines
some options.
The TMR0C is the Timer/Event Counter 0 control regis-
ter, which defines the operating mode, counting enable
or disable and active edge.
There are 3 registers related to the Timer/Event Counter
1; TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing
to TMR1L only writes the data to an internal lower-order
byte buffer (8 bits) and writing to TMR1H will transfer the
specified data and the contents of the lower-order byte
buffer to TMR1H and TMR1L preload registers, respec-
tively. The Timer/Event Counter 1 preload register is
Label (TMR0C)
Bits
Function
T0PSC0~T0PSC2
0~2
Defines the prescaler stages, T0PSC2, T0PSC1, T0PSC0=
000: f
INT
=f
SYS
/2
001: f
INT
=f
SYS
/4
010: f
INT
=f
SYS
/8
011: f
INT
=f
SYS
/16
100: f
INT
=f
SYS
/32
101: f
INT
=f
SYS
/64
110: f
INT
=f
SYS
/128
111: f
INT
=f
SYS
/256
T0E
3
Defines the TMR0 active edge of Timer/Event Counter 0
(0=active on low to high; 1=active on high to low)
T0ON
4
Enable or disable timer 0 counting
(0=disable; 1=enable)
5
Unused bit, read as 0
T0M0
T0M1
6
7
Defines the operating mode (T0M1, T0M0)
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C Register
Label (TMR1C)
Bits
Function
0~2
Unused bit, read as 0
T1E
3
Defines the TMR1 active edge of Timer/Event Counter 1
(0=active on low to high; 1=active on high to low)
T1ON
4
Enable or disable timer 1 counting
(0=disabled; 1=enabled)
5
Unused bit, read as 0
T1M0
T1M1
6
7
Defines the operating mode (T1M1, T1M0)
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C Register