HT48E50
Rev. 0.00
16
September 29, 2004
Preliminary
changed by each writing TMR1H operations. Reading
TMR1H will latch the contents of TMR1H and TMR1L
counters to the destination and the lower-order byte
buffer, respectively. Reading the TMR1L will read the
contents of the lower-order byte buffer. The TMR1C is
the Timer/Event Counter 1 control register, which de-
fines the operating mode, counting enable or disable
and active edge.
The T0M0, T0M1, T1M0, T1M1 bits define the operating
mode. The event count mode is used to count external
events, which means the clock source comes from an
external (TMR0/TMR1) pin. The timer mode functions
as a normal timer with the clock source coming from the
f
INT
clock/instructionclock(Timer0/Timer1).Thepulsewidth
measurement mode can be used to count the high or low
level duration of the external signal (TMR0/TMR1). The
counting is based on the f
INT
clock/instruction clock
(Timer0/Timer1).
In the event count or timer mode, once the Timer/Event
Counter 0/1 starts counting, it will count from the current
contentsintheTimer/EventCounter0/1toFFHorFFFFH.
Once overflow occurs, the counter is reloaded from the
Timer/Event Counter 0/1 preload register and generates
the interrupt request flag (T0F/T1F; bit 5/6 of the INTC) at
the same time.
In the pulse width measurement mode with the
T0ON/T1ON and T0E/T1E bits equal to one, once the
TMR0/TMR1 has received a transient from low to high
(or high to low if the T0E/T1E bits is 0 ) it will start
counting until the TMR0/TMR1 returns to the original
level and resets the T0ON/T1ON. The measured result
will remain in the Timer/Event Counter 0/1 even if the
activated transient occurs again. In other words, only
one cycle measurement can be done. Until setting the
T0ON/T1ON, the cycle measurement will function again
as long as it receives further transient pulse. Note that,
in this operating mode, the Timer/Event Counter 0/1
starts counting not according to the logic level but ac-
cording to the transient edges. In the case of counter
overflows, the counter 0/1 is reloaded from the
Timer/Event Counter0/1 preloadregister and issues the
interrupt request just like the other two modes. To en-
able the counting operation, the timer ON bit
(T0ON/T1ON; bit 4 of TMR0C/TMR1C) should be set to
1. In the pulse width measurement mode, the
T0ON/T1ON will be cleared automatically after the mea-
surement cycle is completed. But in the other two
modes the T0ON/T1ON can only be reset by instruc-
tions. The overflow of the Timer/Event Counter 0/1 is
one of the wake-up sources. No matter what the opera-
tion mode is, writing a 0 to ET0I/ET1I can disable the
corresponding interrupt services.
In the case of Timer/Event Counter 0/1 OFF condition,
writing data to the Timer/Event Counter 0/1 preload
register will also reload that data to the Timer/Event
Counter 0/1. But if the Timer/Event Counter 0/1 is turned
on, data written to it will only be kept in the Timer/Event
Counter 0/1 preload register. The Timer/Event Counter
0/1 will still operate until overflow occurs (a Timer/Event
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Timer/Event Counter 1