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參數資料
| 型號： | HT48E50 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | I/O Type 8-Bit MTP MCU With EEPROM |
| 中文描述： | I / O型8位微控制器帶有EEPROM中期計劃 |
| 文件頁數： | 20/46頁 |
| 文件大?。?/td> | 303K |
| 代理商： | HT48E50 |
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HT48E50
Rev. 0.00
20
September 29, 2004
Preliminary
EECR A.C. Characteristics
Ta=25 C
Symbol
Parameter
V
CC
=5V 10%
V
CC
=2.2V 10%
Unit
Min.
Max.
Min.
Max.
f
SK
Clock Frequency
0
2
0
1
MHz
t
SKH
SK High Time
250
500
ns
t
SKL
SK Low Time
250
500
ns
t
CSS
CS Setup Time
50
100
ns
t
CSH
CS Hold Time
0
0
ns
t
CDS
CS Deselect Time
250
250
ns
t
DIS
DI Setup Time
100
200
ns
t
DIH
DI Hold Time
100
200
ns
t
PD1
DO Delay to 1
250
500
ns
t
PD0
DO Delay to 0
250
500
ns
t
SV
Status Valid Time
250
250
ns
t
HZ
DO Disable Time
100
200
ns
t
PR
Write Cycle Time Per Word
2
5
ms
READ
The READ instruction will stream out data at a specified
address on the DO. The data on DO changes during the
low-to-high edge of SK. The 8 bits data stream is pre-
ceded by a logical 0 dummy bit. Irrespective of the
condition of the EWEN or EWDS instruction, the READ
command is always valid and independent of these two
instructions. After the data word has been read the inter-
nal address will be automatically incremented by 1, al-
lowing the next consecutive data word to be read out
without entering further address data. The address will
wrap around with CS High until CS returns to Low.
EWEN/EWDS
The EWEN/EWDSinstruction will enable or disable the
programming capabilities. At both the power on and
power off state the device automatically enters the disable
mode. Before a WRITE, ERASE, WRAL or ERAL instruc-
tion is given, the programming enable instruction EWEN
must be issued, otherwise the ERASE/WRITE instruction
is invalid. After the EWEN instruction is issued, the pro-
gramming enable condition remains until power is turned
off or an EWDS instruction is issued. No data can be writ-
ten into the EEPROM data memory in the programming
disabled state. By so doing, the internal memory data can
be protected.
ERASE
The ERASE instruction erases data at the specified ad-
dresses in the programming enable mode. After the
ERASE op-code and the specified address have been
issued, the data erase is activated by the falling edge of
CS. Since the internal auto-timing generator provides all
timing signals for the internal erase, so the SK clock is
not required. During the internal erase, we can verify the
busy/ready status if CS is high. The DO will remain low
but when the operation is over, the DO will return to high
and further instructions can be executed.
WRITE
The WRITE instruction writes data into the EEPROM
data memory at the specified addresses in the program-
ming enable mode. After the WRITE op-code and the
specified address and data have been issued, the data
writing is activated by the falling edge of CS. Since the
internal auto-timing generator provides all timing signal
for the internal writing, so the SK clock is not required.
The auto-timing write cycle includes an automatic
erase-before-write capability. So, it is not necessary to
erase data before the WRITE instruction. During the in-
ternal writing, we can verify the busy/ready status if CS
ishigh.TheDOwillremainlowbutwhentheoperationis
over, the DO will return to high and further instructions
can be executed.
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