參數(shù)資料
型號： HSP50216
廠商： Intersil Corporation
英文描述： Four-Channel Programmable Digital DownConverter(四通道可編程數(shù)字下變頻器)
中文描述： 四通道可編程數(shù)字下變頻器（四通道可編程數(shù)字下變頻器）
文件頁數(shù)： 41/52頁
文件大?。?/td> 431K
代理商： HSP50216
3-41
Table of Indirect Read Address (IRA) Registers
The address decoding for the read source locations is given below. The internal address of the data to be read is written to direct
address 3 (ADD(2:0) = 3) to select and/or fetch the data. A strobe is generated, if needed, to fetch or stabilize the data for reading.
If a strobe is needed, the indirect read address must be written to direct address 3 each time the data is needed. If a strobe is not
needed, the data can be read repeatedly at direct addresses 0 and 1(ADD(2:0) = 0 and 1, respectively) with any changes in the
data showing up immediately. The strobe to sample the AGC gain is generated separately by an indirect write (see IWA *00Fh in
the Tables of Indirect Write Address Registers). This allows the AGC gain of all the channels to be sampled simultaneously.
NOTE: These Indirect Read Addresses are repeated for each channel. In the addresses below, the
*
field is the channel select nibble. These bits
of the Indirect Address select the target channel register for the data being read. Values of 0 through 3 and F are valid.
TABLE 43.
μ
P FIFO READ ORDER CONTROL REGISTER (GWA = F820h thru F83Fh)
P(15:0)
FUNCTION
4:0
The five bits selecting the data type are encoded as follows:
C C D D D,
where CC is the channel number and DDD is the data type.
DDD
Data Type
000
I(23:8)
001
I(7:0),8*zeros
010
Q(23:8)
011
Q(7:0),8*zero
100
Mag(23:8)
101
Mag(7:0),8*zero
110
Phase(15:0)
111
AGC gain (15:0)
The upper 16 bits of the I data path via the FIFO/AGC.
The lower 8 bits of the I data path.
The upper 16 bits of the Q data path via the FIFO/AGC.
The lower 8 bits of the Q data path.
The upper 16 bits of magnitude (after the gain adjust described in channel register)
The lower 8 bits of magnitude.
The upper 16 bits of phase.
The upper 16 bits of the AGC gain.
TABLE 44. TABLE OF INDIRECT READ ADDRESS (IRA) REGISTERS
IRA
FUNCTION
*006h
Active Carrier NCO Center Frequency
*00Ch
Wait Preload, Decr 1&2
*009h
Active Timing NCO Center Freq (Most Significant 32 bits)
*00Fh
AGC gain
*100h - *17Fh
Instruction RAMs
*180h - *1FCh
Instruction RAMs (pointer DRAM)
*400h - *43Fh
Coefficient ROM -HBF, const.
*440h - *47Fh
Coefficient RAM -1
*480h - *4FFh
Coefficient RAM -2
*500h - *5FFh
Coefficient ROM -Resampler
F806h
Input Level Detector Output
HSP50216
相關(guān)PDF資料
PDF描述
HSP50307 Burst QPSK Modulator(混合信號QPSK調(diào)制器)
HSP50415VI CABLE ASSEMBLY; 75 OHM TNC MALE TO 75 OHM TNC MALE; 75 OHM, RG6A/U COAX
HSP50415EVAL1 HSP50415EVAL1 Evaluation Kit
HSP9501 Programmable Data Buffer(可編程數(shù)據(jù)緩沖器)
HSP9520 Multilevel Pipeline Registers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HSP50216_06 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital DownConverter
HSP50216_07 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital Downconverter
HSP50216KI 功能描述:上下轉(zhuǎn)換器 MULTI-CHANNEL PROGRAMMABLE DOW CONVERTER,BGA PKG,IND TEMP RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50216KIZ 功能描述:上下轉(zhuǎn)換器 MULTI-CH PROGRAM CONV BGA PKG IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50306 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*