參數(shù)資料
型號: HSP9501
廠商: Intersil Corporation
英文描述: Programmable Data Buffer(可編程數(shù)據(jù)緩沖器)
中文描述: 可編程數(shù)據(jù)緩沖區(qū)(可編程數(shù)據(jù)緩沖器)
文件頁數(shù): 1/8頁
文件大?。?/td> 51K
代理商: HSP9501
3-1
TM
File Number
2786.4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Intersil and Design is a trademark of Intersil Corporation.
Copyright
Intersil Corporation 2000
HSP9501
Programmable Data Buffer
The HSP9501 is a 10-Bit wide programmable data buffer
designed for use in high speed digital systems. Two different
modes of operation can be selected through the use of the
MODSEL input. In the delay mode, a programmable data
pipeline is created which can provide 2 to 1281 clock cycles
of delay between the input and output data. In the data
recirculate mode, the output data path is internally routed
back to the input to provide a programmable circular buffer.
The length of the buffer or amount of delay is programmed
through the use of the 11-bit Length Control Input Port (LC0-
10) and the Length Control Enable (LCEN). An 11-bit value
is applied to the LC0-10 inputs, LCEN is asserted, and the
next selected clock edge loads the new count value into the
Length Control Register. The delay path of the HSP9501
consists of two registers with a programmable delay RAM
between them, therefore, the value programmed into the
Length Control Register is the desired length - 2. The range
of values which can be programmed into the Length Control
Register are from 0 to 1279, which in turn results in an
overall range of programmable delays from 2 to 1281.
Clock select logic is provided to allow the use of a positive or
negative edge system clock as the CLK input to the
HSP9501. The active edge of the CLK input is controlled
through the use of the CLKSEL input. All synchronous timing
(i.e., data setup, hold, and output delays) are relative to the
clock edge selected by CLKSEL. An additional clock enable
input (CLKEN) provides a means of disabling the internal
clock and holding the existing contents temporarily. All
outputs of the HSP9501 are three-state outputs to allow
direct interfacing to system or multi-use busses.
The HSP9501 is recommended for digital video processing
or any applications which require a programmable delay or
circular data buffer.
Features
DC to 32MHz Operating Frequency
Programmable Buffer Length from 2 to 1281 Words
Supports Data Words to 10 Bits
Clock Select Logic for Positive or Negative Edge
System Clocks
Data Recirculate or Delay Modes of Operation
Expandable Data Word Width or Buffer Length
Three-State Outputs
TTL Compatible Inputs/Outputs
Low Power CMOS
Applications
Sample Rate Conversion
Data Time Compression/Expansion
Software Controlled Data Alignment
Programmable Serial Data Shifting
Audio/Speech Data Processing Video/Image Processing
Video/Image Processing
1-H Delay Line of 910 NTSC, 1135 PAL or 1280 Samples:
- High Resolution Monitor Delay Line
- Comb Filter Designs
- Progressive Scanning Display
- TV Standards Conversion
- Image Processing
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
HSP9501JC-25
0 to 70
44 Ld PLCC
N44.65
HSP9501JC-32
0 to 70
44 Ld PLCC
N44.65
HSP9501JC-2596
0 to 70
44 Ld PLCC
Tape and Reel
N44.65
Data Sheet
January 1999
相關PDF資料
PDF描述
HSP9520 Multilevel Pipeline Registers
HSP9520CP Multilevel Pipeline Registers
HSP9520CS Multilevel Pipeline Registers
HSP9521 Multilevel Pipeline Registers
HSP9521CP Multilevel Pipeline Registers
相關代理商/技術參數(shù)
參數(shù)描述
HSP9501_04 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Programmable Data Buffer
HSP9501JC-25 制造商:Rochester Electronics LLC 功能描述:PROGRAMMABLE DATA BUFFER 44 PLCC, 25MHZ, COMM - Bulk
HSP9501JC-2596 制造商:Rochester Electronics LLC 功能描述:- Bulk
HSP9501JC-32 功能描述:緩沖器和線路驅(qū)動器 PROGRAMMABLE DATA BUFFER 44 PLCC, 32MHZ, COMM RoHS:否 制造商:Micrel 輸入線路數(shù)量:1 輸出線路數(shù)量:2 極性:Non-Inverting 電源電壓-最大:+/- 5.5 V 電源電壓-最小:+/- 2.37 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Reel
HSP9512CP WAF 制造商:Harris Corporation 功能描述: