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參數(shù)資料
| 型號： | HSP50216 |
| 廠商： | Intersil Corporation |
| 英文描述： | Four-Channel Programmable Digital DownConverter(四通道可編程數(shù)字下變頻器) |
| 中文描述： | 四通道可編程數(shù)字下變頻器（四通道可編程數(shù)字下變頻器） |
| 文件頁數(shù)： | 27/52頁 |
| 文件大?。?/td> | 431K |
| 代理商： | HSP50216 |
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3-27
Tables of Indirect Write Address (IWA) Registers
Note: These Indirect Write Addresses are repeated for each channel. In the addresses below, the
*
field is the channel select
nibble. These bits of the Indirect Address select the target channel register for the data. Values of 0 through 3 and F are valid. A
channel select nibble value of F is a special case which writes the data to the same location in each of the four channels
simultaneously.
TABLE 1. CHANNEL INPUT SELECT/FORMAT REGISTER (IWA = *000h)
P(15:0)
FUNCTION
15:13
Channel Input Source Selection - Selects as the data input for the channel specified in the Indirect Address either A(15:0), B(15:0),
C(15:0), D(15:0) or the
μ
P Test Input register as shown below.
15:13
000
001
010
011
100
Source Selected
A(15:0)
B(15:0)
C(15:0)
D(15:0)
μ
P Test input register. This is provided for testing and to zero the input data bus when a channel is not in use. The Glo-
bal Write Address register for the
μ
P Test input register is F807h.
12
μ
P Test Register input enable selection
1
0
Select 0 to write test data into the part.
Select 1 to input a constant or to disable the input for minimum power dissipation when an NCO/mixer/CIC section is unused.
Bit 11 of this register is used as the input enable.
A one clock wide pulse generated on each write to lGWA F808h is used as the input enable.
11
μ
P input enable. When bit 12 is set, this bit is the input enable for the
μ
P Test Register input. Active low.
0
1
Enabled
Disabled.
10
Parallel Data Input Format
0
1
Two’s complement
Offset binary
9
Fixed/Floating point
0
1
Fixed point
Floating point. The 16-bit input bus is divided into mantissa and exponent bits grouped either 13/3 or 14/2 depending on
bits 8 and 7. See text.
8:7
Floating point mantissa size select. The 16-bit data input is grouped as a 13/3 or 14/2 mantissa/exponent word. These control bits
select the mantissa/exponent grouping, add an offset to the exponent and set the shift control saturation level.
00
01
10
11
See the exponent tables contained in the Input Select/Format Block Section.
11/3 bits 15:5 mantissa, 2:0 exponent
12/3 bits 15:4 mantissa, 2:0 exponent
13/3 bits 15:3 mantissa, 2:0 exponent
14/2 bits 15:2 mantissa, 1:0 exponent
6:4
De-multiplex control. These control bits are provided to select a channel from a group of multiplexed channels. Up to 8 multiplexed
data streams can be demultiplexed. These control bits select how many clocks after the ENIx signal to wait before taking the input
sample. ENIx should be asserted for one clock period and aligned with the first channel of the multiplexed data set. For example, if
four streams are multiplexed at half the clock rate, ENIx would align with the first clock period of the first stream, the second would
start two clocks later, the next 4 clocks after ENIx, etc. The samples are aligned with ENIx (zero delay) at the input of the
NCO/Mixer/CIC stage at the next ENIx.
000
111
All values from 0 through 7 are valid.
Zero delay
7 clock periods of delay.
HSP50216
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| HSP50216_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital DownConverter |
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| HSP50216KI | 功能描述:上下轉(zhuǎn)換器 MULTI-CHANNEL PROGRAMMABLE DOW CONVERTER,BGA PKG,IND TEMP RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50216KIZ | 功能描述:上下轉(zhuǎn)換器 MULTI-CH PROGRAM CONV BGA PKG IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50306 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
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