- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385396 > HSP50216 (Intersil Corporation) Four-Channel Programmable Digital DownConverter(四通道可編程數(shù)字下變頻器) PDF資料下載
參數(shù)資料
| 型號(hào)： | HSP50216 |
| 廠商： | Intersil Corporation |
| 英文描述： | Four-Channel Programmable Digital DownConverter(四通道可編程數(shù)字下變頻器) |
| 中文描述： | 四通道可編程數(shù)字下變頻器（四通道可編程數(shù)字下變頻器） |
| 文件頁數(shù)： | 22/52頁 |
| 文件大小： | 431K |
| 代理商： | HSP50216 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
3-22
The forward gain consists of a 4-bit exponent and 14-bit
mantissa and an implied 1 for an overall gain of:
0 1.M M M M M M M M M M M M M M * 2
EEEE
.
The gain weighting in dB is approximately:
For a full scale error, the minimum non-zero AGC slew rate
would be approximately 0.0002dB/output or 20dB/sec at
100ksps. The maximum gain would be 6dB/output. This
much gain would probably result in significant AM on the
output.
For median mode, the maximum gain step is approximately.
3dB/output. The step is fixed (it does not decrease as the
error decreases) so a large gain will cause AM on the output
at least that large. The gain should be lowered after the
settling.
The AGC gain limits register sets the minimum and
maximum limits on the AGC gain. The total AGC gain range
is 96dB, but only a portion of the range should be needed for
most applications. For example, with a 16-bit output to a
processor, the 16 bits may be sufficient for all but 24dB of the
total input range possible. The AGC would only need to have
a range of 24dB. This allows faster settling and the AGC
would be at its maximum gain limit except when a high
power signal was received. The AGC may be disabled by
setting both limits to the same value.
The limits are on the forward gain are mapped as:
The AGC loop adjusts its gain to maintain the output signal
magnitude at a level proportional to this set point. There is a
gain of 1.64676 in the I/Q to magnitude computation, so the
threshold should be set to 0.82338 times the desired I/Q
magnitude at the output of the part.
3
1
3
S
3
0
2
S X X X X X X X X X X X X X X X
2
9
1
2
8
0
2
7
1
2
6
2
2
5
3
2
4
4
2
3
5
2
2
6
2
1
7
2
0
8
1
9
9
1
8
0
1
7
1
1
6
2
1
5
3
1
4
1
3
1
2
1
1
1
0
2^
9
8
7
6
5
4
3
2
1
0
Gain Error
(threshold - magnitude)
S = 0 if mag < or = to thresh
S = 1 if mag > thresh
in median mode, the error is set to
SS10000000000000 (
±
2.0)
1 110000000000000
0 010000000000000
Mant mult out
x2
-17
EXP = 0
EXP = 1
EXP = 2
EXP = 4
EXP = 8
EXP = 15
UL, LL
LOAD
READ (
μ
P)
OUTPUT
FORWARD GAIN
S
S
S
S
S
S
S
S
(0) E E E E M M M M M M M M M M M M
(0) E E E E M M M M M M M M M M M M
0
E E E E M M M M M M M M M M M
0
E E E E M M M M M M M M M M M M M M
E E E E M M M M M M M M M M M M M M
S X X X X X X X X X X X X X X X X X X X
S S S S S S S S S S S S S S S S S S S X X X X X X X X X X X X
S S S S S S S S S S S S S S S S S S S X X X X X X X X X X X X
S S S S S S S S S S S S S S S S S S X X X X X X X X X X X X 0
S S S S S S S S S S S S S S S S S X X X X X X X X X X X X 0
S S S S S S S S S S S S S S S X X X X X X X X X X X X 0
S S S S S S S S S S S X X X X X X X X X X X X 0
S S S S X X X X X X X X X X X X 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TBD
E
4
8
E
2
4
E
1
2
E
M M M M M M M M M M M M M M
6
3
1. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0. 0.
5
7
3
1
0
0
0
5
7
8
9
4
2
5
7
3
6
3
5
8
9
4
0
1
1
7
0
0
5
9
0
0
2
9
0
0
1
5
0
0
0
7
0
0
0
4
E
E
E
E M M M M M M M M M M M M
( 0 1. M M M M M M M M M M M M
* 2
EEEE
)
Output (I or Q)
Magnitude
Computed Mag
Threshold
Gain Error
* set MSB to zero.
0.
0.
0.
0.
0.
1
1
1
1
1
2
2
2
2
2
3
3
3
3
3
4
4
4
4
4
5
5
5
5
5
6
6
6
6
6
7
7
7
7
7
8
8
8
8
8
9
9
9
9
9
0
0
0
0
0
1
1
1
1
1
2
2
2
2
2
3
3
3
3
4
4
4
5
5
5
-1.0 to <1.0
0 to 1.414
0 to 2.329
0 to 2.329*
±
2.329
Z
1
1
1
Z
2
2
S
HSP50216
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50307 | Burst QPSK Modulator(混合信號(hào)QPSK調(diào)制器) |
| HSP50415VI | CABLE ASSEMBLY; 75 OHM TNC MALE TO 75 OHM TNC MALE; 75 OHM, RG6A/U COAX |
| HSP50415EVAL1 | HSP50415EVAL1 Evaluation Kit |
| HSP9501 | Programmable Data Buffer(可編程數(shù)據(jù)緩沖器) |
| HSP9520 | Multilevel Pipeline Registers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50216_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital DownConverter |
| HSP50216_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital Downconverter |
| HSP50216KI | 功能描述:上下轉(zhuǎn)換器 MULTI-CHANNEL PROGRAMMABLE DOW CONVERTER,BGA PKG,IND TEMP RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50216KIZ | 功能描述:上下轉(zhuǎn)換器 MULTI-CH PROGRAM CONV BGA PKG IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50306 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。