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參數(shù)資料
| 型號(hào)： | HSP50216 |
| 廠商： | Intersil Corporation |
| 英文描述： | Four-Channel Programmable Digital DownConverter(四通道可編程數(shù)字下變頻器) |
| 中文描述： | 四通道可編程數(shù)字下變頻器（四通道可編程數(shù)字下變頻器） |
| 文件頁數(shù)： | 20/52頁 |
| 文件大?。?/td> | 431K |
| 代理商： | HSP50216 |
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3-20
Wait Preload Register
This register holds the wait counter threshold and two wait
counter decrement values. Each is 10 bits. The wait counter
counts filter input samples until the count is greater than or
equal to the threshold. The wait counter then asserts a flag
to the filter compute engine.
The wait counter threshold is typically set to the total number
of input samples needed to generate a filter output. A "WAIT"
instruction in the filter compute engine waits for the wait
counter flag signal before proceeding. The filter compute
engine would then compute all the filters needed to produce
an output and then would jump back to the "WAIT"
instruction.
The wait counter is implemented with an accumulator. This
allows the count to go beyond the threshold without losing
the sample count. Two bits in the FIR instruction decrement
the wait counter (subtract a value) and select the decrement
value. The decrement value is typically the number of
samples needed for an output (total decimation), though it
can be a different value to ignore inputs and shift the timing.
(The read pointer increment must be adjusted as well.)
The filter compute engine sequencer does not count each
input sample or track whether each filter is ready to run.
Instead, the wait counter is used to determine whether there
are enough input samples to compute all the filters in the
chain and get an output sample from the entire filter chain.
This adds some additional delay since intermediate results
are not precalculated, but it simplifies the filter control. The
number of samples needed is equal to the total decimation
of the filter chain. For example, with two decimate-by-2
halfband filters and a decimate-by-2 shaping FIR, the total
decimation would be 8 so 8 samples are needed to compute
an output. HBF1 would compute four times to generate four
inputs to HBF2. HBF2 would compute twice to generate the
two samples that the shaping FIR needs to compute an
output.
Resampler NCO
The NCO is incremented by the filter compute engine. A bit
in the filter instruction selects whether the NCO is
incremented for that filter output. The center frequency
control is double buffered, i.e., the control word is written to
one register via the
μ
P interface and then transferred to
another (active) register on a write to the TNCF update
strobe location or on a SYNCI (if enabled).
As it is not possible to represent some frequencies exactly
with an NCO and therefore, phase error accumulates
eventually causing a bit slip, the phase accumulator length
has been sized to where the error is insignificant. At an
update rate of 1MHz, half an LSB of error in loading the
56-bit accumulator is 7e-12. After 1 year, the accumulated
phase error is only 0.2e-3 of a bit (<1/10 of a degree).
The NCO update by the filter compute engine is typically at
the resampler's input rate. The NCO then rolls over at a
fraction of the resampler input rate. The output frequency is:
(f
IN
/2
56
)*N.
N should be between 40000000000000h and
FFFFFFFFFFFFFFh (decimation from 1 to 4). The
resampler changes the sample rate by computing an output
or not at each input. If an output is computed, its phase is
shifted based on the NCO phase to slowly slide the timing of
the output relative to the input. The output of the part will be
at the input sample boundaries (except for any FIFOing
following the filter compute engine). If D/A converted directly,
there would be artifacts from the uneven sample spacing,
but if the samples are stored and reconstructed at the proper
rate (the NCO rollover rate), the signal would have only the
distortion produced by interpolation image leakage and the
time quantization due to the limited number of interpolation
filter phases (32).
HSP50216
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| HSP50415VI | CABLE ASSEMBLY; 75 OHM TNC MALE TO 75 OHM TNC MALE; 75 OHM, RG6A/U COAX |
| HSP50415EVAL1 | HSP50415EVAL1 Evaluation Kit |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50216_06 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital DownConverter |
| HSP50216_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Four-Channel Programmable Digital Downconverter |
| HSP50216KI | 功能描述:上下轉(zhuǎn)換器 MULTI-CHANNEL PROGRAMMABLE DOW CONVERTER,BGA PKG,IND TEMP RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50216KIZ | 功能描述:上下轉(zhuǎn)換器 MULTI-CH PROGRAM CONV BGA PKG IND RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50306 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital QPSK Demodulator |
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