9
Test Port Configuration Page
TEST MODE CR4<7:0>
The HSP3824 provides the capability to access a number of
internal signals and/or data through the test port pins TEST
0-7 and TEST_CLK.
(0) Normal Operation Mode
<7:7> Carrier Sense (CRS)
<6:6> Energy Detect (ED)
<5:3> Reserved
<2:2> Initial Detect
<1:0> Reserved
TEST_CLK Internal TX Clock
(1) Correlator Test Mode
<7:0> Correlator Magnitude
TEST_CLK Internal TX Clock (TX chip rate)
(2) Frequency Test Mode
<7:0> Frequency offset Register
TEST_CLK Subsample Clock (Rx symbol rate)
(3) Phase Test Mode
<7:0> Phase
TEST_CLK Subsample Clock (Rx symbol rate)
(4) NCO Test Mode
<7:0> Phase Accum Register (8 most significant bits)
TEST_CLK Subsample Clock (Rx symbol rate)
(5) SQ Test Mode
<7:0> SQ Phase Variance (8 most significant bits)
TEST_CLK Load Signal Quality Signal
(6) Bit Sync Test Mode 1
<7:0> Bit Sync Accum
TEST_CLK Internal RX Clock
(7) Bit Sync Test Mode 2
<7:0> SQ Bit Sync Reference Data (8 most significant bits)
TEST_CLK Load SQ Signal
(8) A/D Cal Test Mode
<7:7> Carrier Sense (CRS)
<6:6> Energy Detect (ED)
<5:5> Reserved
<4:0> A/D Calibrate
TEST_CLK Internal RX Clock
THRESHOLD SETTINGS
A/D CALIBRATION
MODEM STATUS
SIGNAL STATUS
PREAMBLE/HEADER
MODEM CONFIGURATION
I/0 CONFIGURATION
TEST PORT CONFIGURATION
TEST MODE
(0) - NORMAL OPERATION
(8) - A/D CALIBRATION
EXIT
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2:30 PM
BDO:
(1) - CORRELATOR
(2) - FREQUENCY
(3) - PHASE
(4) - NCO PHASE ACC
(5) - SIGNAL QUALITY
(6) - BIT SYNC #1
(7) - BIT SYNC #2
(9) - RESERVED
(9) - RESERVED
(10) - RESERVED
(11) - RESERVED
(12) - RESERVED
(13) - RESERVED
(14) - RESERVED
(15) - RESERVED
Application Note 9615