10
Threshold Settings Page
RECEIVED SIGNAL STRENGTH INDICATION (RSSI)
CR19<5:0>
These control bits are used to specify the RSSI threshold for
measuring and generating the energy detect (ED) signal.
When RSSI exceeds this threshold, ED is declared.
CLEAR CHANNEL ASSESSMENT TIMER CR17<7:0>
This control register is used to configure the period of the
time-out threshold of the CCA watchdog timer.
CLEAR CHANNEL ASSESSMENT CYCLE CR18<7:0>
This control register is used to configure how many times the
CCA timer is allowed to reach its maximum count before it
declares that the channel is clear (independent of the actual
energy measured in the channel).
ENABLE 1/4 CHIP ADJUST DURING ACQUISITION/DATA
CR5<6:6>
This control bit is used to enable/disable 1/4 chip timing
adjustments during acquisition or data.
ACTUAL CLEAR CHANNEL ASSESSMENT TIME
This indication-only field calculates the actual Clear Channel
Assessment Time Out interval (the inner loop).
RECEIVE BIT SYNC AMPLITUDE (ACQUISITION/DATA)
CR22<7:0> CR23<7:0>
These control registers are used to specify the bit sync
amplitude quality threshold used for acquisition and for data.
See typical values in the HSP3824 Datasheet.
RECEIVE PHASE VARIANCE (ACQUISITION/DATA)
CR30<7:0>
CR31<7:0>
These control registers are used to specify the phase
variance quality threshold used for acquisition and for data.
See typical values in the HSP3824 Datasheet (AnswerFAX
doc # 4064).
PREAMBLE/HEADER
MODEM STATUS
SIGNAL STATUS
THRESHOLD SETTINGS
MODEM CONFIGURATION
I/0 CONFIGURATION
TEST PORT CONFIGURATION
EXIT
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A/D CALIBRATION
CCA STYLE
RSSI
CCA TIMER (INNER LOOP)
CCA CYCLE (OUTER LOOP)
1E
2C
03
0001 1110
0010 1100
0000 0011
802.11v1
802.11v2
CCA TIMER
11.264ms
RECEIVER CONFIGURATION
ENABLE SHORT INTEGRATION
ENABLE CHIP ADJUST (DATA)
X
X
X ENABLE CHIP ADJUST (ACQ/DATA)
01E8
0000 0001 1110 1000
00CA
0000 0000 1100 1010
Rx SIGNAL QUALITY #1
Rx SIGNAL QUALITY #2
DURING ACQUISITION
0FFF
0980
0000 1111 1111 1111
0000 1001 1000 0000
DURING DATA
Application Note 9615