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參數(shù)資料
| 型號(hào)： | HSP3824 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類(lèi)： | 無(wú)繩電話/電話 |
| 英文描述： | () |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT |
| 文件頁(yè)數(shù)： | 2/18頁(yè) |
| 文件大小： | 442K |
| 代理商： | HSP3824 |
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2
interfacing with the HFA3724 Intersil IF Quad modem, they
should be set at high impedance.
Digital Data and Clock Interface
This interface is intended to interface with the external digital
data generator and receiver. This is typically for evaluation
purposes with some form of Bit Error Rate Tester (BERT).
The signals of this interface are:
TXD: TX Data; RXD: RX Data; TXC: TX Clock;
RXC: RX Clock.
These signals are available on JP
2
and JP
3
of the evaluation
board and Intersil provides the cable as part of the
evaluation kit.
In addition the output digital Iout an Qout data, as well as the
control and handshaking signals for the TX and RX
operations are available through JP
1
.
For information on the timing and electrical characteristics of
these interface signals refer to the HSP3824 Datasheet.
Test Point Interfaces
A number of signals including signals of the HSP3824 test
port are available for access as test points on the evaluation
board. These signals are available through JP
1
, JP
4
and
JP
5
. For signal pin assignments refer to the attached
schematic of this application note. For the description of
each of the signals refer to the HSP3824 Datasheet.
Jumpers
There are several jumpers on the evaluation board. These
are for connection of the signal inputs to the JP
5
connector
and/or to the SMA input connectors. All jumper options are
indicated on the attached evaluation board schematic.
Test Bed Configuration
Figure 2 illustrates a recommended configuration to be
used for system evaluation of the HSP3824 performance.
In order to make proper BER performance measurements
the waveform needs to be upconverted to some IF
frequency, as a minimum, where noise and interference
sources can be used to evaluate performance. This
configuration is set to evaluate performance based on
continuous transmissions. The user needs to customize a
test bed that is appropriate for packetized data
performance evaluation. The translation to IF and back to
baseband can be accomplished by either using the Intersil
HFA3724 I, Q modem evaluation board or off the shelf
commercially available test equipment. The configuration
example in Figure 2 utilizes the HP8780 signal generator,
the Noise/Com 6108 noise source, the HP8981 vector
analyzer, the HP8657B signal generator, and the Firebert
6000A Bit Error Rate Tester.
HP8780A
VECTOR
SIGNAL
GENERATOR
RF
280MHz
S + N
I
OUT
Q
OUT
BASEBAND DATA
CARRIER
CLOCK
GENERATOR
Q
IN
I
IN
HSP3824
EVAL BOARD
FIREBERD
600A
BER TESTER
CK
RX
BERT
CK
TX
CONTROL PORT
HSP3824
EVAL BOARD
TXQ
TXI
BASEBAND
DATA
NOISE/COM 6108
NOISE ADDER
PAD
BPF
HP8981
VECTOR SIGNAL
ANALYZER
280MHz
RF
HP8657B
SIGNAL
GENERATOR
IBM-PC
CONTROL
CLOCK
GENERATOR
RX
TX
LFP
LPF
CONTROL PORT
FIGURE 2. HSP3824 EVALUATION TEST BED, BASEBAND PROCESSOR EVALUATION CONFIGURATION
PARALLEL PORT
SWITCH
Application Note 9615
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