參數(shù)資料
型號: HSP3824
廠商: HARRIS SEMICONDUCTOR
元件分類: 無繩電話/電話
英文描述: ()
中文描述: TELECOM, CELLULAR, BASEBAND CIRCUIT
文件頁數(shù): 8/18頁
文件大小: 442K
代理商: HSP3824
8
I/O Configuration Page
ALLOW MICROPROCESSOR RATE CHANGE CR1<7:7>
This control bit is used to enable/disable constant data rates
to the external processor that receives the demodulated data
from the HSP3824. Rate changes from DBPSK to DQPSK
within the same packet can be programmed to be
transparent to the external processor.
INVERT TRANSMIT CLOCK PHASE CR9<0:0>
This control bit is used to select the phase of the transmit
output clock.
ASSERT TX_RDY CLOCK COUNT CR1<6:2>
These control bits are used to define the number of clocks
before the first data bit that TX_RDY will be asserted.
Active Signal Levels
These components allow the user to invert the sense of
some signals.
MAC DATA READY (MDRDY) CR9<6:6>
This control bit is used to select the active level of the
MD_RDY signal.
CLEAR CHANNEL ASSESSMENT (CCA) CR9<5:5>
This control bit is used to select the active level of the CCA
signal.
ENERGY DETECT (ED) CR9<4:4>
This control bit is used to select the active level of the ED
signal.
CARRIER SENSE (CRS) CR9<3:3>
This control bit is used to select the active level of the CRS
signal.
TRANSMIT DATA READY (TX_RDY) CR9<2:2>
This control bit is used to select the active level of the
TX_RDY signal.
TRANSMIT POWER ENABLE (TX_PE) CR9<1:1>
This control bit is used to select the active level of the TX_PE
signal.
THRESHOLD SETTINGS
MISCELLANEOUS
A/D CALIBRATION
MODEM STATUS
SIGNAL STATUS
PREAMBLE/HEADER
MODEM CONFIGURATION
I/0 CONFIGURATION
TEST PORT CONFIGURATION
ACTIVE LEVEL
ALLOW MICROPROCESSOR RATE CHANGE
INVERT Tx CLOCK PHASE
INVERT Rx CLOCK PHASE
0
ASSERT TX_RDY
CLOCKS BEFORE DATA
HIGH
LOW
MD_RDY ASSERTION DEFINITION
AFTER CRC-16
AFTER SFD
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
MAC DATA READY (MDRDY)
CLEAR CHAN ASSESSMENT (CCA)
ENERGY DETECT (ED)
CARRIER SENSE (CRS)
Tx DATA READY(Tx_RDY)
Tx POWER ENABLE (TX_PE)
EXIT
DOWNLOAD
2:30 PM
BDO:
Application Note 9615
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