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參數(shù)資料
| 型號(hào)： | HSP3824 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 無(wú)繩電話/電話 |
| 英文描述： | () |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大?。?/td> | 442K |
| 代理商： | HSP3824 |
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7
Symbol Rate
This indication-only field calculates the current receive
symbol rate. It is a function of the Master Clock, Modulation
Type, Chips per Symbol and Rate Divisor.
SPREAD SEQUENCE CR20<7:0> CR21<7:0>
These control registers contain the despreading code for the
I and Q receive paths.
Master Clock
This field allows the user to specify the clock being used to
drive the HSP3824 chip. The clock is operator-entered and
must be manually changed each time the signal generator
frequency is changed. This value is used in formulas for
displays that show frequency or time.
SCRAMBLER TAPS CR16<6:0>
This control register contains the tap configuration for the
transmit scrambler/receive descrambler.
SCRAMBLER SEED CR15<6:0>
This control register contains the seed value for the transmit
scrambler/receive descrambler.
ANTENNA OPERATION CR0<5:5>
This control bit is used to select between full duplex and half
duplex operation.
ANTENNA MODE CR2<2:2>
This control bit is used to select single or dual antenna
mode.
Application Note 9615
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP50016 | Digital Down Converter(數(shù)字式下變頻轉(zhuǎn)換器) |
| HSP50110JI-52 | Digital Quadrature Tuner |
| HSP50110JC-52 | CONN HEADER HM 2MM 100POS |
| HSP50110 | Digital Quadrature Tuner(數(shù)字調(diào)諧器) |
| HSP50210 | Digital Costas Loop(數(shù)字Costas鎖相環(huán)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP3824EVAL | 制造商:Harris Corporation 功能描述: |
| HSP3824VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP3824VI96S5001 | 制造商:Harris Corporation 功能描述: |
| HSP40223221 | 制造商:PARMAR 功能描述:BALLAST HPS/MH 400W 制造商:PARMAR 功能描述:BALLAST, HPS/MH, 400W |
| HSP4070C | 制造商:JLWORLD 制造商全稱:JLWORLD 功能描述:SPEAKER SOUND GENERATORS |
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