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參數(shù)資料
| 型號： | HMS97C8032 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | H8/SLP Series, 38799 Group, 4-ch 14-bit PWM, 2-ch 16-bit TPU, 16-bit AEC, RTC FP-100U; Vcc= 1.8 to 3.6 volts, Temp= -20 to 75 C; Package: PLQP0100KB-A |
| 中文描述： | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, MQFP-80 |
| 文件頁數(shù)： | 66/86頁 |
| 文件大?。?/td> | 1508K |
| 代理商： | HMS97C8032 |
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HMS91C7134
66
November.2001 ver1.0
19.8 Vertical sync. generator
This block generates vertical sync pulses with positive polarity.
This can be done in 3 modes, selectable with VPG. When VPG is
00, the generator operates in the free running mode and the gen-
erated pulse repetition period equals VF x HF x 1/12 MHz clock
period, where VF is a 12 bit value. As a result the frequency of
the free running output sync pulse equals 12 x 106 / HF / VF.
When VPG is 01, the input sync pulse is followed and a substitu-
tion pulse is inserted. In case VPG equals 11, the input sync pulse
is followed but a substitution pulse is disabled, while the incom-
ing sync is missing.
Table 19-6 Modes of the vertical pulse generator
Table 19-7 Free running vertical sync pulse width
19.9 HSYNC / VSYNC output driver
This is output stage for HSYNCout and VSYNCout. It offers out-
put selection, output enabling/disabling and output polarity selec-
tion. With HOPOL and VOPOL the output is selected.
VPG[1:0]
Selected mode
0 0
Free running mode
Period time of vertical pulse generator (= VF)
0 1
The same pulse as the input horizontal sync
Substitution pulse insertion in case of a missing sync pulse
1 0
Reserved
1 1
The same pulse as the input vertical sync
No substitution pulse insertion in case of a missing sync pulse
VOPW[3:0]
Selected mode
0000
2 x t
H(free)
0001
3 x t
H(free)
0010
4 x t
H(free)
-------
Incremented by t
H(free)
1101
15 x t
H(free)
1110
16 x t
H(free)
1111
17 x t
H(free)
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