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參數(shù)資料
| 型號： | HMS97C8032 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | H8/SLP Series, 38799 Group, 4-ch 14-bit PWM, 2-ch 16-bit TPU, 16-bit AEC, RTC FP-100U; Vcc= 1.8 to 3.6 volts, Temp= -20 to 75 C; Package: PLQP0100KB-A |
| 中文描述： | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, MQFP-80 |
| 文件頁數(shù)： | 32/86頁 |
| 文件大小： | 1508K |
| 代理商： | HMS97C8032 |
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HMS91C7134
32
November.2001 ver1.0
11. I/O PORTS
The HMS9xC7134 has four 8-bit ports (Port0, Port1, Port2 and
Port3). Port0 - Port3 are the same as in the 80C51, with the ex-
ception of the additional functions of Port1, Port2 and Port3. All
ports are bidirectional and Pins of which the alternative function
is not used may be used as normal bidirectional I/Os except
Port3.2, Port3.3 and Port3.5(These Pins can be only used as the
output).
The use of Port1- Port3 pins as alternative functions are carried
out automatically by the HMS9xC7134 provided the associated
SFR bit is set HIGH.Port0 is the type of open-drain I/O. Port0.6
and Port0.7 have the capability to drive LED.
Fig. 11.1 shows the port structure.
Figure 11-1 Standard output with the open-drain port
The alternative function for Port1, Port2 and Port3 can be described as follows.
Port 0 : No alternative function.
Port 1 : P1.0 is combined with the SCL1 interface line(open-drain)
P1.1 is combined with the SDA1 interface line (open-drain)
P1.2 is combined with the ACH0 interface line (high-z)
P1.3 is combined with the ACH1 interface line (high-z)
P1.4 is combined with the ACH2 interface line (high-z)
P1.5 is combined with the ACH3 interface line (high-z)
P1.6 is combined with the SCL2 interface line (open-drain)
P1.7 is combined with the SDA2 interface line (open-drain)
Port 2 : P2.0 is combined with the dynamic PWM0 interface line(open-drain or push-pull)
P2.1 is combined with the dynamic PWM1 interface line (open-drain or push-pull)
P2.2 is combined with the static PWM0 interface line (open-drain or push-pull)
P2.3 is combined with the static PWM1 interface line (open-drain or push-pull)
P2.4 is combined with the static PWM2 interface line (open-drain or push-pull)
P2.5 is combined with the static PWM3 interface line (open-drain or push-pull)
P2.6 is combined with the static PWM4 interface line (open-drain or push-pull)
P2.7 is combined with the static PWM5 interface line (open-drain or push-pull)
Port 3 : P3.0 has not alternative function.
P3.1 has not alternative function.
P3.2 is combined with the HSYNCout interface line (push-pull)
P3.3 is combined with the VSYNCout interface line (push-pull)
P3.4 is combined with the PWM6 interface line (open-drain or push-pull)
P3.5 is combined with the CLAMP or PWM7 interface line (push-pull)
P3.6 is combined with the PATOUT interface line (push-pull)
P3.7 is combined with the SOG interface line (pull-up)
I/O PIN
Port Data
Input Data
Special Data / Gnd
Special Function Select
0
1
Enable / Data
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相關(guān)代理商/技術(shù)參數(shù) |
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