參數(shù)資料
型號： HMS97C8032
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： H8/SLP Series, 38799 Group, 4-ch 14-bit PWM, 2-ch 16-bit TPU, 16-bit AEC, RTC FP-100U; Vcc= 1.8 to 3.6 volts, Temp= -20 to 75 C; Package: PLQP0100KB-A
中文描述： 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, MQFP-80
文件頁數(shù)： 62/86頁
文件大小： 1508K
代理商： HMS97C8032
HMS91C7134
62
November.2001 ver1.0
19.5 Horizontal sync. detection
This block extracts the following parameters from the incoming
horizontal or composite sync :
HPER : The number of clock cycles (fSH = 12MHz) be-
tween five sync pulses (4 period time), thus the 12 bits val-
ue HPER will be equal to ((4 x 12 x 106 / fH) - 1) where fH
is the horizontal sync frequency in Hz.
HPOL : The polarity of the sync signal, HPOL will be reset
in case of a positive polarity and set in case of a negative
polarity. The 1/4 point value of HSYNC period time will be
latched for HPOL.
HPRES :To detect the presence of the valid HSYNC sig-
nal, Detector measures the time interval between five sync
pulses (4 period time). No active sync is coming in if the
counter reaches a value of FF0H(4080).
HCHG : The HCHG flag will be set if a change is detected
in either the polarity or the period time. To avoid unintended
setting of the HCHG flag a small deviation in the period time
is allowed.The allowed deviation is approximately 167ns
per line.
19.6 Vertical sync. detection
This block extracts the following parameters from the incoming
vertical sync:
VPER : Either the number of clock cycles (fSV=125kHz
sampling) between two sync pulses(period time). In case
the period time is measured this 12 bits VPER will be equal
to 125 x 103 / fV where fV is the vertical sync frequency in
Hz.
VPOL : The polarity of the sync signal, VPOL will be reset
in case of a positive polarity and reset in case of a negative
polarity. It should be noted here that in case of a composite
sync signal at the input the parameter VPOL will be set al-
ways, disregarding the polarity of the incoming composite
sync. The 1/4 value of incoming VSYNC value will be
latched for VPOL.
VPRES : To detect the presence of the valid VSYNC sig-
nal, Detector measures the time interval between two con-
secutive rising edges of the input signal. No active sync is
coming in if the counter reaches a value of FF0H(4080).
VCHG : The VCHG flag will be set if a change is detected
in either the polarity or the period time. To avoid unintended
setting of the VCHG flag a small deviation in the period
time is allowed.The allowed deviation is approximately
32us per line.
Table 19-2 Threshold frequencies of the presence detector
Detection input
Threshold frequency
HSYNC input
12 KHz
VSYNC input
30 Hz
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