參數(shù)資料
型號(hào)： HMS97C8032
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： H8/SLP Series, 38799 Group, 4-ch 14-bit PWM, 2-ch 16-bit TPU, 16-bit AEC, RTC FP-100U; Vcc= 1.8 to 3.6 volts, Temp= -20 to 75 C; Package: PLQP0100KB-A
中文描述： 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, MQFP-80
文件頁數(shù)： 48/86頁
文件大?。?/td> 1508K
代理商： HMS97C8032
HMS91C7134
48
November.2001 ver1.0
16.5 The RAM Buffer and DDC application
RAM Buffer (RAMBUF) : the RAM buffer can be shared as the system RAM or DDC RAM buffer.
Table 16-3 Description of the EX_DAT and SWENB
Note
1. READ/WRITE through MOVX instruction might conflict with the access from DDC1 hardware. So, the access from
CPU by using MOVX instruction is forbidden.
2. READ/WRITE through DDCADR and RAMBUF registers has the conflicting problem also. Even the content of
DDCADR, which should be employed by DDC1 hardware, will be damaged. So, it is inhibited to use this type of access.
3. If DDCADR reaches 127, it will automatically wrap around to 0 after the access is done.
4. If DDCADR reaches 255, it will automatically wrap around to 0 after the access is done.
5. The access conflicting can be avoided because DDC1 access is done by the interrupt service routine. However, the EDID
transferring from the RAM buffer should be finished within 40 us.
MODE
EX_DAT
0
SWENB
0
DDC1
XRAM : 0 to 127
XRAM : 128 to 255
Normally reserved for DDC1
EDID data
(Note 1, Note 2, Note 3)
Available for the system
access.
(Note 2)
1
0
Normally reserved for DDC1
EDID data
(Note 1, Note 2)
Normally reserved for DDC1
EDID data.
(Note 1, Note 2, Note 4)
0
1
Normally reserved for DDC1
EDID data
(Note 3, Note 5)
Available for the system
access.
1
1
Normally reserved for DDC1
EDID data
(Note 5)
Normally reserved for DDC1
EDID data.
(Note 4, Note 5)
0
1
Normally reserved for DDC2
EDID data
(Note 3)
Available for the system
access.
1
1
Normally reserved for DDC2
EDID data
Normally reserved for DDC2
EDID data.
(Note 4)
DDC2
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