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參數(shù)資料
| 型號： | HMS97C8032 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | H8/SLP Series, 38799 Group, 4-ch 14-bit PWM, 2-ch 16-bit TPU, 16-bit AEC, RTC FP-100U; Vcc= 1.8 to 3.6 volts, Temp= -20 to 75 C; Package: PLQP0100KB-A |
| 中文描述： | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, MQFP-80 |
| 文件頁數(shù)： | 47/86頁 |
| 文件大?。?/td> | 1508K |
| 代理商： | HMS97C8032 |
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HMS91C7134
November.2001 ver1.0
47
Figure 16-4 The conceptual structure of DDC Interface
16.4 DDC2AB/DDC2B+ protocol
DDC2AB/DDC2B+ is a superset of DDC2B. Monitors that im-
plement DDC2AB/DDC2B+ are full featured ACCESS.bus de-
vices. Monitor that implement DDC2B+ uses the same command
set as DDC2AB but cannot use Access.bus device.
Essentially, they are similar to DDC2B. I2C interface forms the
fundamental layer for both protocols. The default address for
monitors is assigned as 6EH other than A0/A1H in DDC2B.
Monitors and hosts can play both the roles of master and slave.
Under this kind of protocol, it is easy to extend the support for
hosts to read VDIF(VESA Video Display Information Format)
and remotely control monitor functions.
Command / Information sequence between host and monitor
must conform to the specification of ACCESS.bus. Timing rules
specified in ACCESS.bus such as maximum response time to
RESET message(< 250 ms)form host, maximum time to hold
SCL low(< 2ms) etc. can be satisfied through software check and
built-in timers such as Timer0, Timer1.
In DDC2AB/DDC2B+, monitor itself can act as a monitor to ac-
tivate the transaction. The default address assigned for host is
50H.
DDC Interrupt
vector address
( 003BH )
DDC2B+/DDC2AB
Utilities
DDC2B
Utilities
DDC1
Utilities
Check Mode flag in DDCCON
Mode = 1 Mode = 1 Mode = 0
I2C
Service Routines
I2C Interface
(H/W)
DDC1 Transmitter
(H/W)
DDC2B+/DDC2AB
command received
DDC2B
command received
SWENB
= 1
SWENB
= 0
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