參數(shù)資料
型號(hào)： HMS97C8032
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： H8/SLP Series, 38799 Group, 4-ch 14-bit PWM, 2-ch 16-bit TPU, 16-bit AEC, RTC FP-100U; Vcc= 1.8 to 3.6 volts, Temp= -20 to 75 C; Package: PLQP0100KB-A
中文描述： 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝： PLASTIC, MQFP-80
文件頁(yè)數(shù)： 38/86頁(yè)
文件大?。?/td> 1508K
代理商： HMS97C8032
HMS91C7134
38
November.2001 ver1.0
14. WATCHDOG TIMER
The hardware watchdog timer (WDT) resets the HMS9xC7134
when it overflows. The WDT is intended as a recovery method in
situations where the CPU may be subjected to a software upset.
To prevent a system reset the timer must be reloaded in time by
the application software. If the processor suffers a hardware/soft-
ware malfunction, the software will fail to reload the timer. This
failure will result in a reset upon overflow thus preventing the
processor running out of control.
In the idle mode the watchdog timer and reset circuitry remain ac-
tive. The WDT consists of a 19-bit counter, the watchdog timer
reset(WDTRST) SFR and watchdog key register(WDT-
KEY).Since the WDT is automatically enabled while the proces-
sor is running. the user only needs to be concerned with servicing
it.The 19-bit counter overflows when it reaches 524288(3FFFH).
The WDT increments once every machine cycle.
This means the user must reset the WDT at least every 524288
machine cycles (524ms @12MHz). To reset the WDT the user-
must write 01EH and then 0E1H to WDTRST. WDTRST is a
write only register. The WDT count cannot be read or written.
The watchdog timer is controlled by the watchdog key register,
WDTKEY. Only pattern 01010101(=55H), disables the watch-
dog timer. The rest of pattern combinations will keep the watch-
dog timer enabled. This security key will prevent the watchdog
timer from being terminated abnormally when the function of the
watchdog timer is needed.
In Idle mode, the oscillator continues to run. To prevent the WDT
from resetting the processor while in Idle, the user should always
set up a timer that will periodically exit Idle, service the WDT,
and re-enter Idle mode.
Table 14-1 Watchdog timer key register (WDTKEY : 0AEH) RESET VALUE:00000000B
Table 14-2 Description of the WDTKEY bits
Table 14-3 Watchdog timer clear register (WDTRST : 0A6H) RESET VALUE:00000000B
Table 14-4 Description of the WDTRST bits
Example Program; Watch Dog Timer
Reset & WDT_refresh Part
Reset:
clr EA
mov PSW, #00
mov SP, #STACK_DATA;
mov WDTKEY, #55h ;
Watchdog stop
WDT_refresh:
mov WDTRST, #1Eh ;
Watchdog timer reset
mov WDTRST, #0E1h ;
Watchdog timer reset
mov WDTKEY, #0F0h ;
Watchdog start
ret
7
6
5
4
3
2
2
0
WDTKEY7
WDTKEY6
WDTKEY5
WDTKEY4
WDTKEY3
WDTKEY2
WDTKEY1
WDTKEY0
BIT
SYMBOL
FUNCTION
7 to 0
WDTKEY7
to
WDTKEY0
Enable or disable watchdog timer.
01010101(=55H) : disable watchdog timer.
others : enable watchdog timer.
7
6
5
4
3
2
2
0
WDTRST7
WDTRST6
WDTRST5
WDTRST4
WDTRST3
WDTRST2
WDTRST1
WDTRST0
BIT
SYMBOL
FUNCTION
7 to 0
WDTKEY7
to
WDTKEY0
Enable or disable watchdog timer.
01010101(=55H) : disable watchdog timer.
others : enable watchdog timer.
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