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參數(shù)資料
| 型號： | HMS97C8032 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | H8/SLP Series, 38799 Group, 4-ch 14-bit PWM, 2-ch 16-bit TPU, 16-bit AEC, RTC FP-100U; Vcc= 1.8 to 3.6 volts, Temp= -20 to 75 C; Package: PLQP0100KB-A |
| 中文描述： | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | PLASTIC, MQFP-80 |
| 文件頁數(shù)： | 37/86頁 |
| 文件大?。?/td> | 1508K |
| 代理商： | HMS97C8032 |
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HMS91C7134
November.2001 ver1.0
37
13. RESET
There are three ways to invoke a reset and initialize the
HMS9xC7134.
Via the external RESET pin
Via the Watchdog Timer overflow
Via low VDD voltage reset
Each reset source will cause an internal reset signal active. The
CPU responds by executing an internal reset and puts the internal
registers in a defined state.
Figure 13-1 The reset mechanism
13.1 External reset
The reset pin RESET is connected to a Schmitt trigger for noise
reduction. A reset is accomplished by holding the RESET pin
LOW for at least 2 machine cycles (24 system clock), while the
oscillator is running.
An automatic reset can be obtained by switching on VDD, if the
RESET pin is connected to GND via a capacitor and to the VDD
via resistor. The capacitor should be at least 10uF.
The increase of the RESET pin voltage depends on the capacitor.
The voltage must remain below the higher threshold for at mini-
mum the oscillator start-up time plus 2 machine cycles.
13.2 Watchdog timer overflow
The length of the output pulse from the WDT is over 2048 machine cycles. In chapter 14, the watchdog timer is described in more detail.
13.3 Low VDD voltage reset
When VDD is below 3.7V, the built-in low voltage detector generates an internal reset signals. The reset signal will be LOW during 2ms
@12MHz after the voltage is higher than 3.7V.
WDT
LVR
S Q
R
2.0ms
Timer
RESET
RSTOUT
CPU&
PERI.
NC
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